For the implementation of large constraint length, sequential Viterbi-Decoders (VD), e.g. for HDSL2 or SDSL, it is necessary to realize the Add-Compare-Select-feedback (ACS-FB) with memories. Using butterfly processor elements (BF-PE) for the ACS computation leads to memory I/O and access conflicts and as a result "ping-pong" architectures are currently implemented, which use twice as much memory than the Viterbi-Algorithm requires. This paper presents a novel path-metric buffering scheme realizing the ACS-FB. It will be proven that this technique is optimal in the sense of routability, area- and power consumption. Memory I/O- and path-metric access conflicts are completely prevented without use of wait-cycles. The introduced architecture always remains the same, regardless to the number of BF-PE and thus simplifies the ACS-unit design for sequential VD macros. Independent from the degree of parallelism only one memory is used and hence the proposed architecture is area- and power efficient.

M. Traber

Papers

A novel ACS-feedback scheme for generic, sequential Viterbi-decoder macros