A time-to-digital-converter-based CMOS smart temperature sensor is proposed for high-accuracy portable applications. Conventional smart temperature sensors rely on an analog-to-digital converter, which consumes much chip area and operating power, for digital output code conversion. For the purpose of cost reduction and power saving, the proposed smart temperature sensor first generates a pulse with a width proportional to the measured temperature. Then, a cyclic time-to-digital converter (TDC) is utilized to convert the pulse into the corresponding digital code. The test chips, with extremely small area of 0.175 mm/sup 2/, were fabricated by the TSMC CMOS 0.35 /spl mu/m 2P4M process. Due to the excellent linearity of the digital output, the achieved measurement error is merely -0.6/spl deg/C to +0.8/spl deg/C without any curvature correction or dynamic offset-cancellation. The effective resolution is better than 0.15/spl deg/C, and the power consumption is 10 /spl mu/W.

A time-to-digital-converter-based CMOS smart temperature sensor

With large-scale integration and increasing power densities, thermal management has become an important tool to maintain performance and reliability in modern process technologies. In the core of dynamic thermal management schemes lies accurate reading of on-die temperatures. Therefore, careful planning and embedding of thermal monitoring mechanisms into high-performance systems becomes crucial. In this paper, we propose three techniques to create sensor infrastructures for monitoring the maximum temperature on a multicore system. Initially, we extend a nonuniform sensor placement methodology proposed in the literature to handle chip multiprocessors (CMPs) and show its limitations. We then analyze a grid-based approach where the sensors are placed on a static grid covering each core and show that the sensor readings can differ from the actual maximum core temperature by as much as 12.6°C when using 16 sensors per core. Also, as large as 10.6p of the thermal emergencies are not captured using the same number of sensors. Based on this observation, we first develop an interpolation scheme, which estimates the maximum core temperature through interpolation of the readings collected at the static grid points. We show that the interpolation scheme improves the measurement accuracy and emergency coverage compared to grid-based placement when using the same number of sensors. Second, we present a dynamic scheme where only a subset of the sensor readings is collected to predict the maximum temperature of each core. Our results indicate that, we can reduce the number of active sensors by as much as 50p, while maintaining similar measurement accuracy and emergency coverage compared to the case where the entire sensor set on the grid is sampled at all times.

https://dl.acm.org/doi/pdf/10.1145/1400112.1400114

Thermal monitoring mechanisms for chip multiprocessors

To explore the possibility of soft intellectual property implementation, a fully digital smart temperature sensor without any full-custom device is proposed for painless VLSI or system-on-chip integrations. The signal is processed thoroughly in time domain instead of conventional voltage or current domain. A cyclic delay line is used to generate the pulse with a temperature-proportional width. The timing reference is just the input clock and a counter instead of voltage or current analog-to-digital converter is utilized for digital output coding. The circuit was implemented by field-programmable gate array chips for functionality verification and performance evaluation. Realized with as few as 140 logic elements, the proposed smart sensor was measured to have an error of -1.5 ~ 0.8 degC over the full commercial IC temperature operation range of 0 degC-75 degC for thermal self-sensing or monitoring. The effective resolution can be made better than 0.1 degC easily, and the power consumption is 8.42 muW at a sampling rate of 2 samples/s. The longest conversion time is around 260 s, and a conversion rate of 3 kHz at least is promised.

A Fully Digital Time-Domain Smart Temperature Sensor Realized With 140 FPGA Logic Elements

High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 °C. This new gate driver prototype has been designed and implemented in a 0.8 μm, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 °C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature (≥220 °C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 μW for operating temperature up to 200 °C.

/pdf/a-200-c-universal-gate-driver-integrated-circuit-for-extreme-1wp89ksnvb.pdf

A 200 °C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

This paper describes a CMOS temperature sensor intended for RFID applications. The sensor achieves an inaccuracy of ±.25°C (3s) from −40°C to 125°C, while using 7× less energy than state-of-the-art sensors with similar accuracy [1]. Its energy efficiency is achieved by the use of a zoom ADC that combines a coarse SAR conversion with a fine ΔΣ conversion, while its accuracy is achieved by the use of various dynamic error correction techniques and a single room-temperature trim.

A CMOS temperature sensor with an energy-efficient zoom ADC and an Inaccuracy of ±0.25°C (3s) from −40°C to 125°C

A Temperature to Digital Converter is described which uses a Sensor based on the principle of switching accurately scaled currents in the parasitic substrate PNP in a standard fine-line CMOS process. The resulting PTAT δV BE signal is amplified in an Auto-Zeroed Switched-Capacitor circuit, sampled and converted to a Digital output by a low power 10 Bit ADC providing a resolution of 0.25 degree from -55 to 125 degrees with an error of less than 1 degree. The paper will focus on the design of the Sensor.

http://ieeexplore.ieee.org/iel5/9916/31525/01470905.pdf

A switched current, switched capacitor temperature sensor in 0.6u CMOS

A 16 bit monolithic D/A converter is described. The device is fabricated with a thin film on CMOS process and uses laser wafer trimming (LWT) to obtain the required performance. The paper briefly discusses design techniques for high resolution D/A converters which have been investigated and describes the circuit finally used.

M. Tuthill

Papers

A switched current, switched capacitor temperature sensor in 0.6u CMOS

A 16 Bit Monolithic CMOS D/A Converter