From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

The state of the art in automatic graph drawing is reviewed, with special attention to the readability of information system diagrams. Existing results in the literature are compared, and a comprehensive algorithmic approach to the problem is proposed. The algorithm presented draws graphs on a grid and is suitable for both undirected graphs and mixed graphs that contain as subgraphs hierarchic structures. Several applications of GIOTTO, a graphic tool that embodies the aforementioned facility, are shown. >

Automatic graph drawing and readability of diagrams

R.E. Bryant proposed a method to handle logic expressions (IEEE Trans. Comp., vol.25, no.8, p.667-91, 1986) which is based on binary decision diagrams (BDD) with restriction; variable ordering ix fixed throughout a diagram. The method is more efficient than other methods proposed so far and depends heavily on variable ordering. A simple but powerful algorithm for variable ordering is developed. The algorithm tries to find a variable ordering which minimizes the number of crosspoints of nets when the circuit diagram is drawn. This is applied to the Boolean comparison of ISCAS benchmark circuits for test pattern generation. The results show that binary decision diagrams (BDD) with the proposed ordering method can verify almost all benchmark circuits in less than several central processor unit (CPU) minutes, which is one hundred times (or more) faster than times reported in the literature. Some techniques for circuit evaluation ordering are also mentioned. >

Evaluation and improvement of Boolean comparison method based on binary decision diagrams

The authors consider the problem of constructing a planar grid embedding for G, where G is a planar graph with n vertices, which maps vertices to distinct grid points and edges to nonintersecting grid paths. A new algorithm is presented that runs in O(n) time and produces grid embeddings with the following properties: (1) the total number of bends is at most 2.4n+2; (2) the number of bends along each edge is at most 4; (3) the length of every edge is O(n); and (4) the area of the embedding is O(n/sup 2/). >

Planar grid embedding in linear time

A popular algorithm to compact VLSI symbolic layout is to use a graph algorithm similar to finding the "longest path" in a network The algorithm assumes that the spacing constraints on the mask elements are of the lower bound type However, to enable the user to have close control over the compaction result, a desired symbolic layout system should allow the user to add either the equality or the upper bound constraints on selected pairs of mask elements as well This paper proposes an algorithm which uses a graph-theoretic approach to solve efficiently the compaction problem with mixed constraints

M. Y. Hsueh

Papers

Symbolic layout and compaction of integrated circuits