A low dropout voltage regulator (LDO) is presented that takes into consideration short channel effects of the pass transistor in suppressing ripples that are present at the input node of the LDO from appearing at the output node of the LDO. The LDO feeds the input ripple voltage to the gate of the pass transistor in such a way that the ripple currents through the pass transistor associated with both the transconductance and the output resistance of the pass transistor are suppressed. In one embodiment, the LDO is provided stability by using only on-chip capacitors. The size of on-chip capacitors is advantageously reduced by connecting a compensation capacitance to an internal node of an error amplifier. The LDO provides stable operation even at small load currents. The LDO also provides good suppression of ripples for a wide range of frequencies.

Low Drop Out Voltage Regulator

A low drop out (LDO) voltage regulator having an error amplifier, a power transistor, a first voltage division unit, a compensation control unit and a compensation bias current source is provided. The error amplifier generates a control voltage according to a first reference voltage and a feedback voltage. The power transistor generates an output voltage at a drain of the power transistor according to the control voltage. The first voltage division unit divides the output voltage to generate the feedback voltage. The compensation control unit generates a compensation control signal to the compensation bias current source according to the control voltage, the output voltage and a compensation bias, so as to make the compensation bias current source generate a compensation bias current, in which the compensation bias is inversely proportional to a supply voltage and ambient temperature.

Low drop out voltage regulator

Apparatus for voltage regulation circuits and related operating methods are provided An exemplary voltage regulation circuit includes a voltage regulation arrangement that provides a regulated output voltage based on an input voltage reference, a phase compensation arrangement coupled to the voltage regulation arrangement and configured to increase a phase margin of the voltage regulation arrangement, and detection circuitry coupled to the phase compensation arrangement The detection circuitry is configured to disable the phase compensation arrangement in response to detecting an output current that is less than a threshold value

Voltage regulation circuitry and related operating methods

A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.

Voltage regulator with improved electrical properties and corresponding control method

Methods and apparatus for a dynamic bias generator are provided. In an example, a dynamic bias generator for a voltage regulator can include a slope generator and a peak detector coupled to the slope generator. In certain examples, the slope generator and the peak detector can receive a representation of output current of the voltage regulator and can adjust a bias control voltage at an output of the peak detector in response to a change in the output current of the voltage regulator.

Low drop out supply asymmetric dynamic biasing

A low-drop out (LDO) regulator circuit is provided having a gate of a pass transistor coupled to an output of an operational transconductance amplifier, the LDO regulator exhibiting a non-dominant pole at an output of the LDO. A dynamic zero-compensation circuit is coupled in parallel to the pass transistor. A compensation control circuit is coupled and configured to adjust a frequency, at which a zero is generated, and cause the generated zero to track with the non-dominant pole.

Madan Mohan Reddy Vemula

Papers

Low dropout regulator