Realising a distributed heterogeneous embedded system using I 2 C requires investigations and findings related to design of networking, architecture, message design and flow for prioritisation, and datagram design. The existing methods for effecting communication among the heterogeneous embedded systems interconnected through I 2 C communication system have not addressed the heterogeneity issues. To suffice, new methods for designing Heterogeneous Embedded networks, communication systems, message flow systems and the message design have presented. The methods have been applied to an existing distributed embedded system and the results obtained proved to be exact as required. Every distributed embedded system is different and the kind of Hardware and protocol conversions required is dependent on the type of distributed embedded system. It has been shown in the paper the kind of conversions that must be undertaken considering I 2 C as the communication method and a set of selected heterogeneous embedded systems that are used for developing an application that monitors and controls the temperatures within a Nuclear reactor system. The way the communication must be effected is dependent on the number of masters and the slaves that must be supported on the network. A communication system architecture that suits the pilot project has been presented. A design flow method which uses priority queues has been presented to effect the communication according to the flow required. The design of datagram required for effecting the communication has also been presented in the paper. The methods have been applied to an existing distributed heterogeneous embedded system that monitors and controls the temperatures with a Nuclear reactor system and the results have been found to be exact fulfilling all the application requirements.

I 2 C Based Networking for Implementing Heterogeneous Microcontroller Based Distributed Embedded Systems

This paper presents a novel architecture of Inter Integrated Circuit (I2C) slave module for embedded processor at protocol level to provide flexibility. The internals of modular description follows higher level of abstraction in Verilog Hardware Description Language (HDL) to provide a technology independent design for Field Programmable Gate Array (FPGA) implementation using Xilinx ISE 12.1. A brief contrast analysis has been carried out from logic synthesis results

/pdf/a-novel-architecture-of-i2c-slave-using-one-hot-encoding-4a42dne467.pdf

A Novel Architecture of I2C Slave using One-Hot Encoding Technique

Old age people suffering from Alzheimer’s disease are not able to carry out their regular medication activities due to decline memory. Taking the correct medicines at regular slots is a challenging task for them. Hence in this research paper, IoT based Medication Assistive System was proposed and developed to facilitate medication adherence. The proposed system incorporates features such as sending a message to a medical practitioner one week ahead to remind the status of medicines and also buzzer beep to ensure the attendance of a candidate which is not available in existing software remainders. It can perform the task even though internet is not available physically by using NodeMCU and Blyank app. The proposed system assists older people in reminding medication timings as well as selection of medicines. It also reduces the dependency of old people on younger generations. Design can be realized at a lower price due to the availability of intelligent programmable hardware at an affordable cost.

IoT and I2C Protocol Based M-Health Medication Assistive System for Elderly People

I2C module is one of the most vital components in lots of chips. A flexible hardware architecture for slave device of I2C protocol is designed in this paper. The designed hardware architecture is divided into two levels: protocol level and application level. The protocol level implements the basic operations of I2C protocol, and the application level, which bases on the protocol level aiming to the demand of various applications. When complete the implementation and simulation of the designed hardware architecture, a verification platform is built to verify the performance of the designed hardware architecture.

A Flexible Hardware Architecture for Slave Device of I2C Bus

The I2C (Inter-Integrated Circuit) protocol is used to attach two devices for communicating with each other in a fast way excluding data losses. With the fast development of Integrated Circuits (ICs) technology, the complication of the circuits has also raised. Therefore, the complexity of the circuit requires self-testability in hardware to palliate the product failure. Built-in-self-test (BIST) is such a technique which can meet the necessity of self-testability with an effective solution over pricy circuit testing system. This paper represents designing and implementation of Inter-Integrated Circuit (I2C) protocol with self-testing ability. The need of programming for setting up a network with two devices is no longer needed in this proposed system. In order to attain compact, stable and reliable data transmission, the I2C is designed with Verilog HDL language and synthesized on Spartan 2 FPGA. An EEPROM and FPGA Spartan 2 are used for the communication testing where the FPGA is master and EEPROM is a Slave.

Design and implementation of a BIST embedded inter-integrated circuit bus protocol over FPGA

To enable devices to communicate with each other over a serial data bus without data loss, as well as to enable faster devices to communicate with slower ones, the I2C(Inter IC) protocol was put forward by Philips Semiconductors in January 2000. Ever since, there has been families of I2C enabled microcontrollers like the PIC18F452 from Atmel and TMS470 from Texas Instruments. However, configuring these microcontrollers requires a lot of programming and knowledge of the register structures, and hence they are not portable. In this paper, a generic design on an FPGA platform is presented, which does away with the need of any further programming while setting up the network. Also, the proposed model can be used both as a master and as a slave. The entire design has been coded in VHDL and verified using Quartus II 6.0.

http://ieeexplore.ieee.org/iel5/5398767/5407062/05407087.pdf

Design and implementation of FPGA based interface model for scale-free network using I2C bus protocol on Quartus II 6.0

This paper proposes a high speed Fast Hartley Transform (FHT) processor using Complex Binary Number System (CBNS). The proposed FHT architecture with the properties of modularity and scalability is well suited for VLSI implementation. The arithmetic computational modules of CBNS-FHT are coded in VHDL through structural modeling style. Simulation of proposed CBNS-FHT processor has been performed on FPGA XC3S700A platform using Xilinx ISE Design Suite 13.4. Comparative analysis of CBNS-FHT with Normal Binary Number System (NBNS)-FHT has been carried out in terms of combinational path delay. Significant improvement in path delay has been observed in CBNS-FHT processor both in terms of FHT coefficients as well as the size of the FHT, leading to the design of a high speed FHT processor.

Design of a High-speed Reconfigurable Fast Hartley Transform Processor using CBNS

This paper focuses on the design of CBNS Nibble Size adder for fast signal processing. A modular based approach has been undertaken both for Pass Transistor as well as Gate Level abstraction. The necessary interconnection between the modules has been done using the structural level design method in Verilog based on conceptual approach for CBNS addition. Simulation, both using ModelSim Altera Starter Edition 6.6d and Xilinx ISE design suite 13.4 confirms the logical verification of the proposed adder. Gate level implementation of the proposed adder on Spartan 3A, XC3S700A FPGA platform reveals 72.8 % reduction in number of LUTs and 51.4 % reduction in path delay over existing CBNS based circuits.

Madhumita Mukherjee

Papers

Design and implementation of FPGA based interface model for scale-free network using I2C bus protocol on Quartus II 6.0

Design and implementation of FPGA based interface model for scale-free network using I2C bus protocol on Quartus II 6.0

Design of a High-speed Reconfigurable Fast Hartley Transform Processor using CBNS

Design of CBNS Nibble Size adder using pass transistor logic circuit: Extension to FPGA implementation

2-D Systolic Array architecture of CBNS based Discrete Hilbert Transform Processor