Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.

Memory array with read/write methods

An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto. The arbitration mechanism comprises (i) a first level of logic for arbitrating between the plurality of standard I/O devices, wherein one standard I/O device is selected from a plurality of the standard I/O devices competing for access to the standard I/O bus, and (ii) a second level of logic for arbitrating between the selected standard I/O device, the CPU and the at least one peripheral device, wherein one of the selected standard I/O device, the CPU and the at least one peripheral device is selected to access the peripheral bus. The arbitration mechanism includes sideband signals which connect the first and second levels of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device.

Arbitration logic for multiple bus computer system

A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (512K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) Use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) Use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the bus small; 5) Use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) use of programmable control register to facilitate run-time bus reconfiguration; 8) Use of spare bus lines to provide local redundancy for the bus; and 9) Use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained.

Defect tolerant integrated circuit subsystem for communication between a module and a bus controller in a wafer-scale integrated circuit system

A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested A power supply network is set up by combining operative power segments A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations Each module is assigned an identity code using discretionary connections

Circuit module redundancy architecture process

A method for improving bandwidth utilization in a packet-switched network via real time control of pause frame transmissions. The invention provides a mechanism whereby a pause frame may be effectively negated if, during the transmission of the pause frame, the network conditions necessitating the pause frame are eliminated or abated. In one Ethernet-compliant embodiment of the invention, monitoring circuitry is provided in a network device to ascertain changes in flow control conditions. Following detection of a flow control condition (e.g., a transmit buffer overflow condition), a flow control unit in the network device initiates transmission of a pause frame. Typically, the initial pause time value will be set to a maximum value (e.g., “FFFF”). During or immediately prior to transmission of the pause frame, the monitoring circuitry functions to monitor the state of the flow control unit or flow control enablement signals to determine if the flow control condition remains in effect. If the monitoring circuitry determines that the flow control condition has been negated, the status of the pause frame transmission is then determined. If the pause time value has not been transmitted, the monitoring circuitry causes a reduced pause time value (e.g., “0000”) to be transmitted, thereby effectively negating potentially deleterious effects on network bandwidth that might otherwise result from the original pause frame. In an alternate embodiment of the invention, if the monitoring circuitry determines that the flow control condition giving rise to the pause frame has been negated, the frame check sequence/cyclic redundancy check value at the end of the pause frame is invalidated.

Real time control of pause frame transmissions for improved bandwidth utilization

A method and apparatus for fault tolerant communication among a plurality of I/O controllers and a communication controller using an I/O bus having byte-parallel and bit-serial data lines. Each controller is connected to the bit-serial and byte-parallel data lines and the CPU communication controller is capable of selectively indicating which set of lines shall be used for communicating information. When serial communication is desired, a switching signal is transmitted by the CPU communication controller on the serial data line whereupon the I/O controllers switch communication from the byte-parallel data lines to the bit-serial data line. Serial arbitration conflicts are avoided by allocating a time interval to each I/O controller. Each time interval is divided into 3-bit periods. An arbitrating I/O controller asserts the first itself bit true, asserts the second bit false, and disconnects from the bus during the third bit period to separate in time the modules connected to the bus from each other. The CPU communication controller in an operating system initializes newly-inserted modules and synchronizes unsynchronized modules by generating a signal on the bus for prescribed periods of time after which synchronizing control modules within each I/O controller synchronizes the I/O controller with the rest of the system.

Method and apparatus for fault tolerant communication within a computing system

PURPOSE:To obtain an information transferring system having a fault resistance by instructing selectively a means for executing an information transfer by a byte parallel format, and a means for executing an information transfer by a bit series format, and executing the information transfer. CONSTITUTION:When a parallel bus consisting of plural, for instance, eight pieces of data (CAD) lines 148 is being operated normally, data are sent and received by a byte parallel format between plural input/output control devices 128. A series bus consisting of a series data line 140 for transmitting the data by a bit series format between plural devices 128 is operated, when a fault has been detected in a byte parallel line. A CPU communication control device 124 is connected to a bit series line and a byte parallel line, and indicates selectively whose group line is to be used for transferring the information. It is executed by sending a transaction provided with a correct CRC code, to the device 128 through the series bus, when it is desired to execute a series operation, and when the device 128 receives it, the parallel bus is switched to the series bus. In this way, information of a fault resistance can be transferred.

Maikeru Jiei Furemonto

Papers

Method and apparatus for fault tolerant communication within a computing system

Information transmission system