A microcontroller ( 100 ) has a CPU ( 102 ) and memory ( 104 ). Memory ( 104 ) contains a memory array ( 200 ). A large portion of the array ( 200 ) is used to contain functional data for the CPU ( 102 ), but the array ( 200 ) also contains one or a few rows of memory content parity information. Once the array ( 200 ) is written with lasting data and/or software, a parity controller ( 208 ) will generate initial parity values which correlate to the contents of the memory array ( 200 ). This parity information is stored within the parity portion of the array ( 200 ). After generating the initial parity data, the parity controller ( 208 ) occasionally, upon some parity checking event, generates current parity from the data stored within the array ( 200 ). This current parity is compared against the parity portion of the array ( 200 ) using the parity logic ( 210 ). If errors are detected, it is clear that the software/data that was intended to be static and non-changing has experienced a leakage error, soft error event, electrical short, etc. Once these errors are detected corrective measures may be taken to extend the reliable life of the product.

On-chip error detection and correction system for an embedded non-volatile memory array and method of operation

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Memory Module With Reduced Access Granularity

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of complementary data signals. The pair of data signals are also supplied to a driving gate means which outputs a signal corresponding to at least one data signal of the pair of data signals supplied thereto. The driving gate means also comprises at least one try-state gate controlled by a clock signal. An output signal of the driving gate means is held by a memory means, and also outputted as complementary output signals.

Flip-flop circuit

A circuit (40) constructed in accordance with this invention includes a ring oscillator (25) to provide a signal which is dependent on the propagation delays of the inverters (33, 34, 35) comprising the ring oscillator, therefore the frequency of the ring oscillator is inversely dependent upon the propagation delays of the inverter comprising the ring oscillator. Means (37) are provided to determine the propagation delay introduced by the components in the ring oscillator by measuring the frequency of the output signal produced by the ring oscillator which provides a signal to a multiplexer (36) which selects among a number of preset delay components (26) those components which are necessary to ensure that the propagation delay caused by the circuitry (not shown) connected to the input lead (21) of the circuit constructed in accordance with this invention plus the propagation delay introduced by the selectable delay elements is nearly a constant propagation delay.

Delay control circuit

An MOS transistor circuit contains at least one "zero" threshold mode transistor to provide a power-down function for the circuit. The "zero" threshold mode transistor is connected between an enhancement-mode MOS driver transistor and a depletion-mode MOS load transistor.

MOS Transistor circuit with a power-down function

A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected respectively in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above the drain of the first insulation gate FET transistor, and the second polycrystalline silicon layer is provided above the drain of the second insulation gate FET transistor.

Static memory having load polysilicon resistors formed over driver FET drains

A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected, respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.

MOS Static RAM layout with polysilicon resistors over FET gates

This protected MOS transistor circuit has a p-type semiconductor substrate, VSS terminal, input MOS transistor, first resistor connected to the gate electrode of transistor, and MOS transistor which has a gate electrode connected to the VSS terminal and a current path connected between the VSS terminal and a junction of the first resistor and the gate electrode of the input MOS transistor. This protected MOS transistor circuit further has a second resistor connected in series with the first resistor, and pn-junction diode connected reversely between the VSS terminal and the junction of the first and second resistors.

Protected MOS transistor circuit

A semiconductor circuit has first and second MOS transistors which are connected between an output terminal and a positive and a reference power source terminal, respectively, a bootstrap capacitor connected between the output terminal and the gate of the first MOS transistor, an inverter which inverts the input signal and which supplies the inverted signal to the gate of the second MOS transistor after a predetermined delay timne, and a switching MOS transistor having a current path connected between the input terminal and the gate of the first MOS transistor. The switching MOS transistor has a threshold voltage greater than that of the second MOS transistor.

Makoto Segawa

Papers

MOS Transistor circuit with a power-down function

Static memory having load polysilicon resistors formed over driver FET drains

MOS Static RAM layout with polysilicon resistors over FET gates

Protected MOS transistor circuit

MOSFET buffer circuit with an improved bootstrapping circuit