AES algorithm or Rijndael algorithm is a network security algorithm which is most commonly used in all types of wired and wireless digital communication networks for secure transmission of data between two end users, especially over a public network. This paper presents the hardware implementation of AES Rijndael Encryption and Decryption Algorithm by using Xilinx Virtex-7 FPGA. The hardware design approach is entirely based on pre-calculated look-up tables (LUTs) which results in less complex architecture, thereby providing high throughput and low latency. There are basically three different formats in AES. They are AES-128, AES-192 and AES-256. The encryption and decryption blocks of all the three formats are efficiently designed by using Verilog-HDL and are synthesized on Virtex-7 XC7VX690T chip (Target Device) with the help of Xilinx ISE Design Suite-14.7 Tool. The synthesis tool was set to optimize speed, area and power. The power analysis is made by using Xilinx XPower Analyzer. Pre-calculated LUTs are used for the implementation of algorithmic functions, namely S-Box and Inverse S-Box transformations and also for GF (28) i.e. Galois Field Multiplications involved in Mix-Columns and Inverse Mix-Columns transformations. The proposed architecture is found to be having good efficiency in terms of latency, throughput, speed/delay, area and power.

FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption

Security of Wireless Sensor Networks (WSNs) is a very crucial factor when deployed for reconnaissance in sensitive areas. The existing symmetric encryption schemes provide a good amount of security, but maintenance of keys is difficult. When asymmetric schemes are used, maintenance of keys is easier, but they provide a lesser degree of security when compared to symmetric encryption schemes. In order to cope up with these shortcomings, we propose to use an improved version of the hybrid encryption scheme, which is a combination of Advanced Encryption Standard (AES) and Elliptical Curve Cryptography (ECC) with cross encrypted keys for secure key exchange and node authentication and hybrid encryption for enhanced cipher-text security. In case of transmission in WSNs, Statistical Cooperative Diversity based on Alamouti code is the most commonly used transmission scheme. However, for an arbitrary number of sensors, Alamouti code limits the BER performance and energy is not distributed equally, thereby creating the energy-hole problem which leads to early dysfunction of the sensors and may eventually lead to dysfunction of the Wireless Sensor Network (WSN). Extended Cooperative Space-time Block Codes (ECBSTBCs), which are obtained from Alamouti code, have the same characteristics of Alamouti code with the energy being distributed equally among the active sensors. With these factors in mind, we propose to use ECBSTBC as the transmission scheme. The improved hybrid scheme is ideal for ECBSTBC based WSN due to the speed of operation and higher degree of security that it offers.

An improved AES-ECC hybrid encryption scheme for secure communication in cooperative diversity based Wireless Sensor Networks

Wi-Fi protected access 2 WPA2 is considered one of the most secure protocols employed in wireless local area networks WLANs. This is despite of having significant security vulnerabilities. The aim of this paper is two-fold. Firstly it analyses the WPA2 security protocol and presents its weaknesses in detail. Secondly it presents a methodology that demonstrates how the WPA2 security protocol can be fully exposed by malicious attacks. Importantly, proposals on how to enhance its security are offered.

Exposing WPA2 security protocol vulnerabilities

Due to the advantages of pay-on-demand, expand-on-demand and high availability, cloud databases (CloudDB) have been widely used in information systems. However, since a CloudDB is distributed on an untrusted cloud side, it is an important problem how to effectively protect massive private information in the CloudDB. Although traditional security strategies (such as identity authentication and access control) can prevent illegal users from accessing unauthorized data, they cannot prevent internal users at the cloud side from accessing and exposing personal privacy information. In this paper, we propose a client-based approach to protect personal privacy in a CloudDB. In the approach, privacy data before being stored into the cloud side, would be encrypted using a traditional encryption algorithm, so as to ensure the security of privacy data. To execute various kinds of query operations over the encrypted data efficiently, the encrypted data would be also augmented with additional feature index, so that as much of each query operation as possible can be processed on the cloud side without the need to decrypt the data. To this end, we explore how the feature index of privacy data is constructed, and how a query operation over privacy data is transformed into a new query operation over the index data so that it can be executed on the cloud side correctly. The effectiveness of the approach is demonstrated by theoretical analysis and experimental evaluation. The results show that the approach has good performance in terms of security, usability and efficiency, thus effective to protect personal privacy in the CloudDB.

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An effective approach for the protection of privacy text data in the CloudDB

The requirement of information security on network has become more and more important. Cryptography is a method to provide information confidentiality, authenticity and integrity. There are so many challenges to implement cryptography algorithm such as execution time, memory requirement, and computation power. Parallel computation is a promising technique to improve the performance of cryptography algorithm. Mainly divide-and-conquer strategy is used in parallel computation to solve the algorithms in parallel by partitioning and allocating, number of given subtask to available processing units. Parallel computation can be performed using multicore processors by parallelizing the execution of algorithm in multiple cores. In this paper we explore the implementation of AES (Advanced Encryption Algorithm) cryptography algorithm on dual core processor by using OpenMP API to reduce the execution time.

Performance Improvement of Advanced Encryption Algorithm using Parallel Computation

Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). ModelSim SE PLUS 5.7g software is used for simulation and optimization of the synthesizable VHDL code. Synthesizing and implementation (i.e. Translate, Map and Place and Route) of the code is carried out on Xilinx - Project Navigator, ISE 8.2i suite. All the transformations of both Encryption and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. Xilinx XC3S400 device of Spartan Family is used for hardware evaluation. This paper proposes a method to integrate the AES encrypter and the AES decrypter. This method can make it a very low-complexity architecture, especially in saving the hardware resource in implementing the AES (Inv) Sub Bytes module and (Inv) Mix columns module etc. Most designed modules can be used for both AES encryption and decryption. Besides, the architecture can still deliver a high data rate in both encryption/decryption operations. The proposed architecture is suited for hardware-critical applications, such as smart card, PDA, and mobile phone, etc.

Mangesh S. Deshpande

Papers

FPGA implementation of AES encryption and decryption