The finite impulse response (FIR) filters are one among the digital filters which are widely proposed in field programmable gate array implementations. This paper presents the design of 4-tap and 8-bit fast low-pass FIR filter design under FPGA background using hardware description language (HDL). This design leads many applications like biomedical signals, pattern recognition, image processing and communications fields. The main attention of this FIR filter is focused towards the noise and performance constraints. In light of FPGA to accomplish FIR filter, not just considered the fixed capacity DSP-explicit chip constant, yet in addition the DSP processor adaptability. The blend FPGA and DSP innovation can further improve integration, increment work speed and framework abilities.

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Field Programmable Gate Array (FPGA)-Based Fast and Low-Pass Finite Impulse Response (FIR) Filter

In the field of VLSI, enhancement is prominent. Arithmetic circuits are one of the influential sectors in today’s end products of electronics, where multipliers are one of the deciding factors of efficiency. Multiplier plays an important role in different applications such as digital signal processing in which it acts as a key hardware block. As time rolls down, the technology exposed the ways for the initiation of many hardware and software implementations of the faster multipliers. One among them is the Montgomery multiplier. The fundamental operation in the Montgomery multiplier is the modular multiplication. It is mainly used in FIR filters, which in-turn has numerous applications such as speech analysis, multi-rate signal processing, adaptive filters, and averaging filters. With the usage of proposed compressor in the conventional design of the multiplier, the number of transistor count has been declined by a significant amount and made the design into an optimal area design. This paper presents a modified Montgomery multiplier design and its implementation in the 5th order FIR filter. The entire design simulation is carried out using CMOS and PTL logic in 45 nm technology. There is an escalation in the result outcomes, and the multiplier has an area efficiency of 65% and a power reduction of about 68% in comparison with conventional design.

High Performance, Low Power Architecture of 5-stage FIR Filter using Modified Montgomery Multiplier

From the dawn of the VLSI based approach for the digital signal processing at most research is centered upon the digital filters and their designing, as filters are the circuit elements which are mainly used in signal processing where among these digital filters the group of filters that have finite duration of impulse response are called FIR(finite impulse response) filters and are having the preference over other groups of filters in the classification as their linearity and standard signal processing characteristics are conducive for implementing in microprocessors and DSP’s(digital signal processor). As the ever-changing reforms in technology take place, a system with reconfigurable design has to be provided in order to cope up with the transitions in the research timeline and since there have been many years of ongoing research in the branch of FIR filters with reconfigurable design an analysis of this research is presented by studying the design approach and proposed architectures by various researchers from the last 20 years.

Reconfigurable FIR Filters: A survey

Finite Impulse Response (FIR) Filter is filtering whose impulse response is of finite duration. A Higher order of FIR filter is required for meeting precise frequency specification in several digital signal processing applications. But the number of additions and multiplications increase linearly with filter length leading to computational complexity. So a less complex Multiple Constant Multiplication design techniques are used for designing FIR filter in which given input is multiplied with the set of constants. It basically reduces the number of additions required for realization of multiplication. Thus it is suitable for large order FIR filter with fixed coefficients. Block processing along with transpose form of FIR filter is used to support pipelining and higher sampling rate. Power efficient Spartan 6 FPGA logic family is used for hardware implementation. Thus implemented structure provides an area and power efficient high-performance design of FIR filter with reduced computational complexity for both fixed and reconfigurable application.

Manish B. Trimale

Papers

FIR filter implementation on FPGA using MCM design technique