Showing papers by "Manuel P. Malumbres published in 2016"

Design of a Computerised Flight Mill Device to Measure the Flight Potential of Different Insects

Abstract: Several insect species pose a serious threat to different plant species, sometimes becoming a pest that produces significant damage to the landscape, biodiversity, and/or the economy. This is the case of Rhynchophorus ferrugineus Olivier (Coleoptera: Dryophthoridae), Semanotus laurasii Lucas (Coleoptera: Cerambycidae), and Monochamus galloprovincialis Olivier (Coleoptera: Cerambycidae), which have become serious threats to ornamental and productive trees all over the world such as palm trees, cypresses, and pines. Knowledge about their flight potential is very important for designing and applying measures targeted to reduce the negative effects from these pests. Studying the flight capability and behaviour of some insects is difficult due to their small size and the large area wherein they can fly, so we wondered how we could obtain information about their flight capabilities in a controlled environment. The answer came with the design of flight mills. Relevant data about the flight potential of these insects may be recorded and analysed by means of a flight mill. Once an insect is attached to the flight mill, it is able to fly in a circular direction without hitting walls or objects. By adding sensors to the flight mill, it is possible to record the number of revolutions and flight time. This paper presents a full description of a computer monitored flight mill. The description covers both the mechanical and the electronic parts in detail. The mill was designed to easily adapt to the anatomy of different insects and was successfully tested with individuals from three species R. ferrugineus, S. laurasii, and M. galloprovincialis.

Shared Memory Tile-Based vs Hybrid Memory GOP-Based Parallel Algorithms for HEVC Encoder

Abstract: After the emergence of the new High Efficiency Video Coding standard, several strategies have been followed in order to take advantage of the parallel features available in it. Many of the parallelization approaches in the literature have been performed in the decoder side, aiming at achieving real-time decoding. However, the most complex part of the HEVC codec is the encoding side. In this paper, we perform a comparative analysis of two parallelization proposals. One of them is based on tiles, employing shared memory architectures and the other one is based on Groups Of Pictures, employing distributed shared memory architectures. The results show that good speed-ups are obtained for the tile-based proposal, especially for high resolution video sequences, but the scalability decreases for low resolution video sequences. The GOP-based proposal outperforms the tile-based proposal when the number of processes increases. This benefit grows up when low resolution video sequences are compressed.

Impact of dead zone size on the rate/distortion performance of wavelet-based perceptual image encoders

Abstract: When using uniform quantization schemas with dead zone, the final R/D performance may be affected by two parameters, (a) the dead zone size, and (b) reconstruction point location inside each quantization step. In this work we analyze how the dead zone size affects the image quality for wavelet based encoders that have been perceptually enhanced by using the Contrast Sensitivity Function (CSF). Since the application of CSF may change the distribution of wavelet coefficients in each quantization step, and particularly in the dead zone surroundings, choosing appropriate values for both quantization parameters, dead zone size and reconstruction point, may introduce benefits in terms of R/D performance. After a thorough study about the effects of both parameters, we observed that tuning a variable dead zone quantizer with optimum dead zone and reconstruction point values, rate savings up to 7.7% can be obtained when comparing with popular uniform or fixed dead zone quantizers.

Evaluation of an HEVC hardware IME module using a SoC platform

Abstract: In the HEVC standard, motion estimation is one of the most complex task of the video encoder, requiring a great percentage of the encoding time mainly due to (a) a large set of Coding Tree Unit partitioning modes, (b) the presence of multiple reference frames, and (c) the varying size of Coding Units in comparison with its predecessor H264/AVC. In addition, HEVC adopts Variable Block Size Motion Estimation to obtain advanced coding efficiency. In this work, we evaluate a hardware IME design when applied to an System-On-Chip platform. In this evaluation we will measure the impact on the Rate/Distortion performance when applying different CTU sizes and reference search areas. Furthermore, we will evaluate the effect of the DMA transfers required in the computational performance. This architecture has been synthesized and implemented on the Xilinx SoC, Zynq-7 Mini-ITX Motherboard XC7Z100 (xc7z100ffg900-2). We have evaluated our hardware IME design using different CTU size configurations, search area sizes and DMA burst sizes in order to determine the maximum speed gain respect to the HEVC reference software. Results show that (a) the overall encoding time could be reduced by 588 times, being the DMA transfer the bottleneck of our design; (b) Rate/Distortion performance has no significant variations when using different CTU and search area configurations; (c) the encoding delay will strongly depend on the size of both CTU and search area sizes.