A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

High frequency analog transistors, method of fabrication and circuit implementation

A method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate (26) having at least two features e.g. a polysilicon land (36), another polysilicon land (48), and substrate (26),thereon whereat it is desired to make electrical connections; forming a layer (54) of etch stop material having a first etch characteristic over each of the features; forming a layer (56) of dielectric material having a second etch characteristic over each of the features; simultaneously etching at least two vias (58, 66, 60) through the layer of dielectric material using an etchant selective to the layer of dielectric material so as to substantially stop on the layer of etch stop material, the at least two vias including a via over each of the features; and extending the vias through the layer of etch stop material so as to expose the features for subsequent electrical connections (76, 74, 78).

Method of forming contacts to a semiconductor device

The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ region layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base an insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

Fabrication methods for high performance lateral bipolar transistors

A process is disclosed with integrated steps for fabricating bipolar and CMOS transistors. Mask, patterning and implanting steps are highly integrated to reduce the fabrication complexity. The integrated steps include a split level polysilicon step wherein PMOS and NMOS gate conductors and a bipolar emitter structure is formed. The polysilicon is heavily doped which forms MOS transistor gate electrodes, and another high impurity concentration area which is later diffused into an underlying bipolar base region. Small area, high performance transistors can be fabricated with laterally extending contact strips. Alignment of electrode metallization patterns is thus less critical.

Integrated bipolar and CMOS transistor with titanium nitride interconnections

A method of fabricating MESFET devices having a submicron line gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of angled evaporation at least one gate wall within said resist cavity, the gate wall defining a shaped gate cavity; depositing gate electrode material within the gate cavity, and removing the resist material. In one embodiment of the invention the gate wall is removed from the gate electrode material, leaving a free-standing electrode. In another embodiment, the gate wall is a permanent part of the electrode structure.

Fabrication of metal lines for semiconductor devices

A process is provided for manufacturing bi-polar transistors integrated on silicon. To form transistors of very small dimensions, a layer of polycrystalline silicon is deposited (after a localized oxidization step) which is etched and which is doped so as to serve as doping source for P+ extrinsic base regions of the transistor. After doping of the P intrinsic base, the oxide and/or nitride is then deposited at low pressure which is implanted with an impurity facilitating dissolution thereof. On the vertical walls of the polycrystalline silicon around the base, the nitride is not dissolved. Elsewhere it is easily dissolved. Advantage is taken of the oxide or nitride thickness which remains to form by diffusion of an N+ emitter region which will not extend laterally as far as the P+ type extrinsic base but which will allow to remain an intrinsic base of very small thickness. The emitter diffusion may take place through a second polycrystalline silicon layer.

Process for manufacturing integrated bi-polar transistors of very small dimensions

L'invention concerne la fabrication de transistors bipolaires integres sur silicium. The invention relates to the manufacture of bipolar transistors integrated on silicon. Pour faire des transistors de tres petites dimensions, on commence par deposer du silicium polycristallin (apres une etape d'oxydation localisee) que l'on grave et que l'on dope pour qu'il serve de source de dopant pour des regions de base extrinseque P + (44) du transistor. To make transistors with very small dimensions, one begins by depositing polysilicon (after a localized oxidation step) that is etched and that is doped to serve as the dopant source for the base regions extrinsic P + (44) of the transistor. Apres dopage de la base intrinseque P (48), on depose ensuite de l'oxyde et/ou du nitrure (52) a basse pression que l'on implante avec une impurete facilitant sa dissolution. After doping of the intrinsic P base (48), then removal of the oxide and / or nitride (52) at low pressure which is implanted with an impurity facilitating its dissolution. Sur les parois verticales du silicium polycristallin autour de la base, le nitrure n'est pas dissous. On the vertical walls of polysilicon around the base, the nitride is not dissolved. Ailleurs il se dissout facilement. Elsewhere it dissolves easily. On profite de l'epaisseur d'oxyde ou de nitrure qui subsiste pour former par diffusion une region d'emetteur N + (56) qui ne s'etendra pas lateralement jusqu'a la base extrinseque (44) de type P + mais qui laissera subsister une base intrinseque (48) de tres faible epaisseur. Advantage is taken of the oxide or nitride thickness remaining for forming by diffusion an emitter N + region (56) does not extend laterally to the extrinsic base (44) of P + -type but let remain an intrinsic base (48) of very small thickness. La diffusion d'emetteur peut se faire a travers une deuxieme couche de silicium polycristallin (54). The emitter diffusion can be done through a second polysilicon layer (54).

Method of making integrated bipolar transistors of very small dimensions

L'INVENTION CONCERNE LA FABRICATION DE TRANSISTORS BIPOLAIRES INTEGRES SUR SILICIUM POUR FAIRE DES TRANSISTORS DE TRES PETITES DIMENSIONS, ON COMMENCE PAR DEPOSER DU SILICIUM POLYCRISTALLIN (APRES UNE ETAPE D'OXYDATION LOCALISEE) QUE L'ON GRAVE ET QUE L'ON DOPE POUR QU'IL SERVE DE SOURCE DE DOPANT POUR DES REGIONS DE BASE EXTRINSEQUE P 44 DU TRANSISTOR APRES DOPAGE DE LA BASE INTRINSEQUE P 48, ON DEPOSE ENSUITE DE L'OXYDE ETOU DU NITRURE 52 A BASSE PRESSION QUE L'ON IMPLANTE AVEC UNE IMPURETE FACILITANT SA DISSOLUTION SUR LES PAROIS VERTICALES DU SILICIUM POLYCRISTALLIN AUTOUR DE LA BASE, LE NITRURE N'EST PAS DISSOUS AILLEURS, IL SE DISSOUT FACILEMENT ON PROFITE DE L'EPAISSEUR D'OXYDE OU DE NITRURE QUI SUBSISTE POUR FORMER PAR DIFFUSION UNE REGION D'EMETTEUR N 56 QUI NE S'ETENDRA PAS LATERALEMENT JUSQU'A LA BASE EXTRINSEQUE 44 DE TYPE P MAIS QUI LAISSERA SUBSISTER UNE BASE INTRINSEQUE 48 DE TRES FAIBLE EPAISSEUR LA DIFFUSION D'EMETTEUR PEUT SE FAIRE A TRAVERS UNE DEUXIEME COUCHE DE SILICIUM POLYCRISTALLIN 54

Marcel Roche

Papers

Process for manufacturing integrated bi-polar transistors of very small dimensions

Method of making integrated bipolar transistors of very small dimensions

Procede de fabrication de transistors bipolaires integres de tres petites dimensions