The Internet-of-Things (IoT) is the future of the Internet, where everything will be connected. Studies have revealed that fog/edge computing-based services will play a major role in extending the cloud by carrying out intermediary services at the edge of the network. Fog/edge computing-based IoT’s (FECIoT) distributed architecture enhances service provisioning along the Cloud-to-Things continuum, thereby making it suitable for mission-critical applications. Furthermore, the proximity of fog/edge devices to where the data is produced makes it stand-out in terms of resource allocation, service delivery, and privacy. From the business perspective, FECIoT will lead to a boom and spring up of small-to-medium-sized enterprises, thereby encouraging inclusion for all. To this end, we present a comprehensive survey on state-of-the-art IoT literature over the period 2008–2018 and propose the FECIoT framework which covers the enabling technologies, services, and open research issues. A tutorial approach is employed, progressing from basic to more advanced concepts within the IoT domain. Lastly, we show how FECIoT can be deployed in real-life cyber-physical systems, such as the intelligent transportation system, smart grid, smart health-care, smart homes, and smart environment.

Fog/Edge Computing-Based IoT (FECIoT): Architecture, Applications, and Research Issues

Coefficient multipliers are the stumbling blocks in programmable finite impulse response (FIR) digital filters. As the filter coefficients change either dynamically or periodically, the search for common subexpressions for multiplierless implementation needs to be performed over the entire gamut of integers of the desired precision, and the amount of shifts associated with each identified common subexpression needs to be memorized. The complexity of a quality search is thus beyond the existing design algorithms based on conventional binary and signed digit representations. This paper presents a new design paradigm for the programmable FIR filters by exploiting the extended double base number system (EDBNS). Due to its sparsity and innate abstraction of the sum of binary shifted partial products, the sharing of adders in the time-multiplexed multiple constant multiplication block of the programmable FIR filters can be maximized by a direct mapping from the quasi-minimum EDBNS. The multiplexing cost can be further reduced by merging double base terms. Logic synthesis results on more than one hundred programmable filters with filter taps ranging from 10 to 100 and coefficient word lengths of 8, 12, and 16 bits show that the average logic complexity and critical path delay of the programmable FIR filters designed by our proposed algorithm have been reduced by up to 47.81% and 14.32%, respectively over the existing design methods.

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Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System

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Structure and Interpretation of Computer Programs, 2nd Ed by Abelson and Sussman, with Sussman, MIT Press, 1996, ISBN 0-262-51087-1, 657pp.

In this contribution, we present a coverage driven functional verification environment based on the UVM framework and the System Verilog language to certify the operational correctness of the ECC error management logic used in volatile and nonvolatile memories. We apply this methodology to floatinggate nonvolatile memories for the embedded market, which requires a read error rate of 10−14. The proposed environment achieves the complete validation of ECC features by 80 coverage main points. Additionally, we cover also the error distribution in the cache buffer, on board the memory, which requires additional 240 coverage points. The advantage of code reusability of this kind of verification environment and the wished coverage plan, achieved in few minutes with respect to the exhaustive approach, make easier the application of the proposed solution to any kind of volatile and nonvolatile memories.

UVM-based verification of ECC module for flash memories

This paper describes the architecture and design of a Bluetooth Low Energy Controller. The designed controller consists of a hardware and software part.

Architecture and design of a Bluetooth Low Energy Controller

This paper presents a verification architecture of the Bluetooth Low Energy Link Layer Controller. The tested controller is a hardware implementation of the lower layers, described in the Bluetooth Low Energy Specification. The designed test bench uses a UVM methodology and constrained random verification techniques to meet the expected functional coverage metrics.

UVM-based Verification of Bluetooth Low Energy Controller

This paper discusses the regression testing in digital integrated circuit verification. The aim of the metric-driven verification (MDV) and its role in modern verification methodology is presented. According to recognized limitations, it is proposed to include the regression testing strategy in verification environment itself. The data collected from the verification metrics can be used to adjust the testing procedures during the simulation. This approach allows for a dynamic management of the regression testing structure and may result in a significant reduction of the simulation time. The presented solution introduces a concept of the test segments. They may be started at arbitrary simulation point related to the DUT internal state (checkpoint). Usage of such segments, in the controlled regression testing strategy, may prevent from repeating the stimuli which is not contributing to the pre-defined verification metrics.

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Metric-Driven Verification Methodology with Regression Management

Functional Coverage is a mechanism used in digital integrated circuits functional verification to measure whether the executed test set covered the declared functionality. It helps to examine test scenarios, by providing metrics that give information about the testcase or design-under-test (DUT) reached states (coverage points). SystemVerilog language provides dedicated syntax to make it possible, such as covergroup and coverpoint objects. However, these features have very limited functionality. It is difficult to manipulate functional coverage data on the testbench level, e.g. to make the test scenario dependent on the real-time coverage metrics. It is also not clear how to define coverage objects for complex design features. The architecture of a new, object-oriented functional coverage mechanism for digital verification, implemented in Python, is proposed in this paper. The testbench is based on the Cocotb open verification framework. The implemented solution gives more flexibility than standard SystemVerilog syntax and enables more agile creation of verification environments.

New architecture of the object-oriented functional coverage mechanism for digital verification

This paper presents an FPGA-based design and implementation of a universal multiplier-accumulator unit. The proposed structure is based on an idea of parallel multiplication of properly aligned data stored in FPGA on-chip memory used as a cyclic buffer. The example application was implemented in Altera Cyclone II device and worked as a hardware accelerator of digital FIR filter. The results show that the higher performance for high-order FIR filter operation may be achieved in Altera Cyclone II family FPGAs in comparison to modern digital signal processors.

Marek Cieplucha

Papers

UVM-based Verification of Bluetooth Low Energy Controller

Architecture and design of a Bluetooth Low Energy Controller

Metric-Driven Verification Methodology with Regression Management

New architecture of the object-oriented functional coverage mechanism for digital verification

High performance FPGA-based implementation of a parallel multiplier-accumulator