Showing papers by "Marek Perkowski published in 2000"

A minimal universal test set for self-test of EXOR-Sum-of-Products circuits

Abstract: A testable EXOR-Sum-of-Products (ESOP) circuit realization and a simple, universal test set which detects all single stuck-at faults in the internal lines and the primary inputs/outputs of the realization are given. Since ESOP is the most general form of AND-EXOR representations, our realization and test set are more versatile than those described by other researchers for the restricted GRM, FPRM, and PPRM forms of AND-EXOR circuits. Our circuit realization requires only two extra inputs for controllability and one extra output for observability. The cardinality of our test set for an n input circuit is (n+6). For Built-in Self-Test (BIST) applications, we show that our test set can be generated internally as easily as a pseudorandom pattern and that it provides 100 percent single stuck-at fault coverage. In addition, our test set requires a much shorter test cycle than a comparable pseudoexhaustive or pseudorandom test set.

New multivalued functional decomposition algorithms based on MDDs

Abstract: This paper presents two new functional decomposition partitioning algorithms that use multivalued decision diagrams (MDDs). MDDs are an exceptionally good representation for generalized decomposition because they are canonical and they can represent very large functions. Algorithms developed in this paper are for Boolean/multivalued input and output, completely/incompletely specified functions with application to logic synthesis, machine learning, data mining and knowledge discovery in databases. We compare the run-times and decision diagram sizes of our algorithms to existing decomposition partitioning algorithms based on decision diagrams. The comparisons show that our algorithms are faster and do not result in exponential diagram sizes when decomposing functions with small bound sets.

Layout-driven synthesis for submicron technology: mapping expansions to regular lattices

Abstract: This paper introduces a basic concept in VLSI layout which can nd applications to submicron design, quantum devices, and designing new ne-grain digital, analog and mixed FPGAs. This concept is called Lattice Structure and it extends the concepts from [8] and [1, 13, 14, 16, 17]. In a regular arrangement of cells, every cell is connected to 4, 6 or 8 neighbors and to a number of vertical, horizontal and diagonal buses. Methods for expanding arbitrary binary, multivalued, and analog functions to this layout are illustrated. Introduction. Every signal in our layout, a Lattice, can be treated as continuous or multi-valued (particularly, binary). A multivalued connection for logic with 2 values can be realized by k binary wires that go together (making the lattice "fat") and encode the multi-valued signal to binary. The well-known: Fat Trees, Generalized PLAs, Maitra cascades, and Akers Arrays [1, 4, 17] structures are only few special cases of this powerful concept. Our regular structure concept extends also some structures that exist in several patents of ne grain FPGAs (Motorola, Atmel [2], Plessey, Pilkington), but in addition we show constructive and e cient methods of designing discrete and continuous functions in these structures. We showed on many examples, [8, 10, 13, 14, 16, 17, 20] that this geometry is very powerful and better than the previously investigated general cellular structures. Here we will further extend and unify these notions to expansions with more than 2 successor functions, and geometries with more than 4 neighbors. In theory the lattices can be extended to any number of neighbors of a cell, but 8 is practically enough. The fundament of our approach are expansions of functions, i.e. operators that transform a function to few simpler functions. There are two types of expansions: canonical (such as Shannon) and noncanonical (such as Sum-ofProducts expansion). Also, the expansions can be characterized as of maximum-type, or of Linearly-Independent type. Maximum type expansions are generalizations of Shannon (S) [18], Post [10], and Sum-of-Products (SOP) [15] expansions. Linearly Independent expansions are generalizations of Davio expansions [18], and are for arbitrary algebras that have at least one linear operation, but most often are based on the algebraic structure of a eld [6, 7, 8, 9, 10, 11, 13, 14]. These expansions are next mapped to neighborhood structures that are more powerful than those investigated theoretically in the past [1, 4], but similar to those from commercial Fine Grain FPGAs, [2]. The concept of a lattice diagram involves three components: (1) expansion of a function (the function corresponds to the initial node in the lattice), which creates several successor nodes of this node, (2) joining of several nodes of a tree's level to a single node, which is in a sense a reverse operation to the expansion, (3) a regular geometry to which the nodes are mapped, this geometry guides which nodes of the level are to be joined. Below, we will present new geometries, expansions, and joinings operations on nodes. We will illustrate these concepts with just few simple examples of applications. Layout Geometries. In case of 4 neighbors (Fig. 1a,c,d,g) the lattice is planar and based on a rectangular grid. Each cell has two inputs (from N and E) and two outputs (to S and W), [1, 4, 17, 20]. Our structure generalizes the known switch realizations of symmetric binary functions [1, 4], based on Shannon expansion, but it allows also for Positive and Negative Davio expansions [18], negated variables and constants as control variables of the nodes, nodes controlled by not variables but functions, and inverted edges between nodes. Lattice diagram counterparts of Kronecker [7], Pseudo-Kronecker [18] and Free Diagrams can be realized for functions. It can be shown [8] that every function that is not symmetric can be symmetrized by repeating variables in the lattice layers, and the selection of the next variable is done using the Repeated Variable Maps from [12]. With respect to possible technological realization, the condition of only a single control variable in a level [4, 14] is no longer required, and all three types of buses (vertical, horizontal and diagonal) are used to lead any variable to the circuit's levels. Similarly we do not always require the existence of the diagonal buses, as well as the condition of having only constant values on the envelope of the circuit, or having the outputs only on the envelope. Now, arbitrary variables can occur on the envelope, and outputs can be taken from the middle by use of buses (this is an approach from commercial Fine Grain FPGAs [2]). Moreover, pairs or triplets of binary control variables can be used in nodes for arbitrary Linearly-Independent expansions [10]. Or equivalently, multivalued controls are used. In short, for a 4-neighbor lattice geometry, any canonical form of ReedMuller logic and its Linearly Independent generalizations can a b c d a b b c c c d d

Self-repairable EPLDs: design, self-repair, and evaluation methodology

Abstract: This paper describes the concept of self-testable and self-repairable EPLDs (Electrically Programmable Logic Devices) for high security and safety applications. A design methodology is proposed for self-repairing of a GAL (Generic Array Logic) which is a kind of EPLD. Our fault-locating and fault-repairing architecture uses universal test sets, fault-detecting logic, and self-repairing circuits with spare devices. The design method allows to detect, diagnose, and repair all multiple stuck-at faults which might occur on E/sup 2/CMOS cells in programmable AND plane. A "column replacement" method with extra columns is introduced that discards each faulty column entirely and replaces it with an extra column. The evaluation methodology proves that the self-repairable GAL will last longer in the field.