A data transfer control device using USB (a first bus), the end of a data phase (data transport: transfer of all the data) during an OUT transaction is determined on condition that data transmission (DMA transfer) through EBUS (a second bus) has ended, and the end of a data phase during an IN transaction is determined on condition that data reception through EBUS has ended and also an Empty signal has gone active, indicating that a data storage area has become empty. A counter that counts the data size is provided on the EBUS side. If data reception through EBUS ends and the size of data remaining in the data storage area is less than the maximum packet size, a short packet in the data storage area is transmitted automatically through USB and an interrupt is used to notify the firmware of the presence of the short packet.

Data transfer control device, electronic equipment, and data transfer control method

The present invention generally relates to a dilator with a curved tip. The curved tip is machined through a specific range of diameters so that a physician can establish the diameter of the opening with the dilator inserted. The angle of the dilator also allows the physician to access the interspinous ligament through a minimally invasive opening in the patients back, minimizing the trauma caused to surrounding body tissue.

Curved dilator and method

A method for reducing memory latency in a multi-node architecture In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined The home node initiates a read to memory to complete the speculative read request Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued

Method and apparatus for reducing memory latency in a cache coherent multi-node architecture

Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols.

Memory system and operating method thereof

Dynamic arbitration based on a high priority transaction type. A first memory access request is received at a first request queue. If the first memory access request is of a first type, the priority of the first request queue is dynamically raised over the priority of a second request queue. The priority of the second request queue is dynamically raised over that of the first request queue when requests of the first type in the first request queue, up to a maximum predetermined number of requests, have been serviced.

Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type

A bridge logic unit provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to memory bus, and a peripheral device coupled to a peripheral bus, such as a PCI bus. To maintain coherency, the bridge logic unit disables write posting in certain specific situations, and flushes posted write transactions before allowing certain read requests to be serviced. More specifically, in one embodiment when a PCI device performs a read to main memory, which may be implemented within the bridge as delayed read, the bus bridge blocks CPU to PCI transactions and flushes any posted CPU to PCI transactions pending in the bridge. The bus bridge enables CPU to PCI posting after the pending CPU to PCI transactions have been flushed and after the snoop phase of a snoop cycle corresponding to the memory read operation completes. In a further embodiment, prior to performing a PCI read cycle on behalf of a read cycle initiated by the microprocessor, the bus bridge determines whether any PCI to memory transactions are pending in the PCI slave transient write buffer. If any posted write transactions reside in the PCI slave transient write buffer, the bus bridge retries the read cycle on the processor bus and blocks any subsequent posting of write transactions to memory from the PCI bus. When the pending PCI to memory transactions have been flushed from the PCI slave transient write buffer, and the microprocessor reattempts the read, the read cycle is initiated on the PCI bus. At this point, PCI to memory write posting is re-enabled.

System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations

A computer is provided having a bus interface unit coupled between a CPU bus and a mezzanine bus, or PCI bus. The bus interface unit includes a plurality of input buffers which can be selectively connected and disconnected in a dynamic fashion according to active and inactive signals forwarded thereto. Signals forwarded to the bus interface unit from the CPU are classified according to the transaction phase of CPU bus activity. If signals associated with one particular transaction phase are active, then input buffers attributed to signals of other transaction phases can be deactivated. It is preferred that input buffers associated with signals of a request and arbitration phase be maintained active and coupled to power regardless of the present transaction phase unless the computer enters a powered down mode, such as sleep, idle or standby.

Device and method for dynamically reducing power consumption within input buffers of a bus interface unit

To assure that memory and/or I/O cycles will run correctly after a PCI device configuration cycle that changes memory and/or I/O mapping, in a multi-processor P6 computer system that pipelines instructions. The memory and I/O cycles are suspended on the processor bus until the configuration cycle has been completed. A signal is generated within the address decode logic to prevent address decoding from taking place if a PCI device is being configured. During the configuration transactions, other pipelined transaction cycles are snoop stalled until the PCI configuration write has been completed.

Preventing corruption in a multiple processor computer system during a peripheral device configuration cycle

A bridge logic unit includes a CPU interface coupled to a CPU bus, a PCI interface
coupled to a PCI bus, and an AGP interface coupled to an AGP bus. The interfaces
communicate with each other through a non-local memory queue manager. The non-local
memory queue manager advantageously includes an AGP arbiter for arbitrating between
requests requiring ownership of the AGP bus initiated by the CPU and PCI devices. The
AGP bus arbiter employs a round-robin arbitration algorithm to arbitrate between
contending requests received from the CPU bus and the PCI bus. If no requests are
pending from either of the buses, the AGP arbiter parks on the CPU bus by asserting an
acknowledge signal to the CPU interface. Thus, the bus arbiter may advantageously
accommodate low latency accesses to the AGP bus by the microprocessor. Furthermore,
in order to optimize multiple burst transfer requests. another control signal (referred to as
LastAddrReq) may by generated by each requesting interface. The LastAddrReq signal
indicates that a particular request is the last request corresponding to a burst transaction on
the associated bus. Once a requesting interface wins arbitration. the AGP arbiter parks on
the winning interface and does not allow another interface to win arbitration until it detects
the LastAddrReq signal asserted from the current owner of the bus. In this manner, burst
cycles may advantageously be effectuated uninterrupted. Furthermore, the CPU interface
can gain exclusive access to either the PCI bus or AGP bus through the use of a LOCK
signal. If the CPU interface asserts the LOCK signal with the assertion of CPU_AGPREQ,
and the PCI or AGP bus arbiter grants an acknowledge to the CPU interface, the CPU
interface will win all further arbitration cycles until it deasserts LOCK with its next
assertion of CPU_AGPREQ, thus giving high priority to the CPU interface.

Computer system including arbitration mechanism allowing multiple bus masters to access a graphics bus

A computer system includes a bridge logic unit for interfacing between a
microprocessor coupled to a processor bus, a first peripheral device coupled to a first
peripheral bus such as a PCI bus, and a main memory coupled to a memory bus.
Additional peripheral buses may further be connected to the bridge logic unit. The bridge
logic unit includes a respective interface for each bus from which a memory request may
be initiated. For example, the bridge logic unit may include a CPU interface configured
to receive memory requests from the microprocessor, and a PCI interface configured to
receive memory requests from a PCI bus peripheral. and an AGP interface configured to
receive memory requests from an AGP/PCI bus peripheral. Additional interfaces are
provided for any further buses supported by the system. A memory queue manager is
coupled to receive memory requests from each of the interfaces and to provide the requests
to a memory controller independent of the source of the request. In one embodiment, the
memory queue manager includes a read request queue for receiving memory read requests,
and a write request queue for receiving memory write requests. A queue arbiter is
provided to arbitrate among requests from the various interfaces to determine a particular
request which should be loaded within one of the queues (i.e., either the read request queue
or the write request queue) of the memory queue manager. The queue arbiter is configured
to take only a single request at a time from each interface. and implements a round-robin
arbitration algorithm.

Maria L. Melo

Papers

System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations

Device and method for dynamically reducing power consumption within input buffers of a bus interface unit

Preventing corruption in a multiple processor computer system during a peripheral device configuration cycle

Computer system including arbitration mechanism allowing multiple bus masters to access a graphics bus

Computer system including bridge logic having a fair arbitration mechanism to support isochronous devices