M
Mário P. Véstias
Researcher at Instituto Superior de Engenharia de Lisboa
Publications - 102
Citations - 752
Mário P. Véstias is an academic researcher from Instituto Superior de Engenharia de Lisboa. The author has contributed to research in topics: Field-programmable gate array & Deep learning. The author has an hindex of 11, co-authored 93 publications receiving 538 citations. Previous affiliations of Mário P. Véstias include INESC-ID & Polytechnic Institute of Lisbon.
Papers
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Proceedings ArticleDOI
Trends of CPU, GPU and FPGA for high-performance computing
Mário P. Véstias,Horácio C. Neto +1 more
TL;DR: In this article, the authors compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains, showing that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from highperformance computing with intensive floating-point calculations.
Journal ArticleDOI
A survey of convolutional neural networks on edge with reconfigurable computing
TL;DR: Reconfigurable computing is being considered for inference on edge due to its high performance and energy efficiency while keeping a high hardware flexibility that allows for the easy adaption of the target computing platform to the CNN model.
Journal ArticleDOI
Moving Deep Learning to the Edge
TL;DR: This paper reviews the main research directions for edge computing deep learning algorithms and suggests new resource and energy-oriented deep learning models, as well as new computing platforms.
Proceedings ArticleDOI
Decimal multiplier on FPGA using embedded binary multipliers
Horácio C. Neto,Mário P. Véstias +1 more
TL;DR: This paper introduces a novel approach to the design of a decimal multiplier in FPGA using the embedded arithmetic blocks and a novel method for binary to BCD conversion and results indicate that the proposed binary toBCD converter is more efficient than the traditional shift and add-3 algorithm.
Proceedings ArticleDOI
Parallel decimal multipliers using binary multipliers
Mário P. Véstias,Horácio C. Neto +1 more
TL;DR: This paper analyzes the tradeoffs involved in the design of a parallel decimal multiplier, for decimal operands with 8 and 16 digits, using existent coarse-grained embedded binary arithmetic blocks and indicates that the proposed parallel multipliers are very competitive when compared to decimal multipliers implemented with direct manipulation of BCD numbers.