A low power management system including both hardware (Figure 2) and software (Figure 5) is provided for a battery powered portable computer (not shown). The low power management system powers down various sections (10, 12, 16, 21, 24) of the computer (DMA, VCO, DISPLAY, UART) when they are not used. The low power management system is controlled by a control program directing the microprocessor (40) (Figure 2) of the computer, and includes the capability to turn off clock signals (not shown) to the various sections of the computer based upon demand. Also included is the capability to turn on clock signals based upon demand. The low power management system also includes the capability to turn on the computer upon a press of a key on the computer keyboard. The low power management system monitors software application programs for keyboard activity so as to turn off the microprocessor in the computer in response to a loop (10, 16) looking for a keypress and certain other loops which can be monitored without use of the microprocessor.

Computer power management system

An event driven wake-up system for controlling current consumption by a microcontroller that controls a data input device used to enter data to a data processing system is provided. The wake-up system include a data input device, such as a keyboard, that is responsive to an external event, such as depression of a key on the keyboard, by providing a signal indicative of the occurrence of the external event. The microcontroller responds to the external event by generating a data character that corresponds to the signal received from the data input device and provides that data character to the CPU of the data processing system. The microcontroller includes means for sensing inactivity at the data input device and for entering the microcontroller into a reduce current consumption mode when such inactivity is sensed. Wake-up logic responds to an input signal from the data input device and/or from the data processing system when the microcontroller is in the reduced current consumption mode by providing a wake-up signal that removes the microcontroller from the reduced current consumption mode.

Event driven scanning of data input equipment using multi-input wake-up techniques

A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem, the slow refresh clock is terminated and the system memory and video memory are again refreshed using a normal faster clock.

Slow memory refresh in a computer with a limited supply of power

A multi-buffering apparatus in a random number generator. A microprocessor includes a random number generator that employs multiple buffers for buffering random data bytes generated by the generator. The apparatus maintains a first selector for selecting one of the buffers as the current buffer for filling with generated bytes. When the current fill buffer becomes full, the apparatus updates the first selector to a different buffer and continues the process until all buffers are full. The apparatus maintains a second selector for selecting one of the buffers as the current buffer for supplying random data bytes to an application. When the current supply buffer becomes empty, the apparatus updates the second selector to a different buffer and continues the process until all buffers are empty. The apparatus can concurrently fill the buffer selected by the fill selector and supply data from the buffer selected by the supply selector.

Continuous multi-buffering random number generator

A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes. The various hardware options responsive to the hardware parameters include allowing for various bus interfaces, trimming the time constant of an analog RC circuit which provides internal bus timing strobes, switching internal timing strobes to external pads for output, switching external timing strobes from external pads to replace the internal strobes, and floating the outputs of all output pad drivers for junction leakage tests.

Device and method for programming critical hardware parameters

A clock circuit for a microcomputer having a clock input, a halt mode state output and an interrupt input, comprises: a clock pulse generator having an output, a switch for applying a pulsed output to the interrupt input of the microcomputer to indicate a start of operation; a latch receptive of the output of the switch to change from a first state to a second state, gates receptive of the output of the clock pulse generator and the latch for applying clock pulses to the microcomputer when the logic is in the second state and preventing the application of clock pulses to the microcomputer when the logic is in the first state and circuitry for applying the halt mode state output to the logic circuit to disable same from the second state to the first state.

Method and circuit for controlling single chip microcomputer

A portable test strip reading instrument having a microcomputer (10), a battery power source (9) and analog (12) and digital (20) circuitry, the improvement comprising an analog voltage regulator (22) and a digital voltage (21) regulator for the analog and digital circuitry, and means controlled by the microcomputer (10) for turning off the analog regulator when the analog circuitry is not utilized.

Circuitry for a portable test strip reading instrument

A sensor-integrator circuit having a sensor for producing a current varying in accordance with the sensed parameter or a reference current source, a comparator having inverting and noninverting inputs and an output and charge storage device coupled to the inverting input. The circuit is energized to obtain a given positive steady state reset voltage, a reference voltage is applied to the noninverting input of a comparator which is less positive than the steady state voltage and integration is initiated solely by alternately applying the current from the sensor and the reference current to the inverting input of the comparator.

Mark C. Loessel

Papers

Method and circuit for controlling single chip microcomputer

Circuitry for a portable test strip reading instrument

Sensor integrator system

Microcompute clock circuit