ion and Compositional Techniques From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 E.Allen Emerson, Richard J. Trefler Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Dirk W. Hoffmann, Thomas Kropf Abstract BDDs: A Technique for Using Abstraction in Model Checking . . . 172 Edmund Clarke, Somesh Jha, Yuan Lu, Dong WangBDDs: A Technique for Using Abstraction in Model Checking . . . 172 Edmund Clarke, Somesh Jha, Yuan Lu, Dong Wang Theorem Proving Related Approaches Formal Synthesis at the Algorithmic Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Christian Blumenröhr, Viktor Sabelfeld Xs Are for Trajectory Evaluation, Booleans Are for Theorem Proving . . . . . 202 Mark Aagaard, Thomas Melham, John O’Leary Verification of Infinite State Systems by Compositional Model Checking . . 219 K.L.McMillan Symbolic Simulation/Symbolic Traversal Formal Verification of Designs with Complex Control by Symbolic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Gerd Ritter, Hans Eveking, Holger Hinrichsen Hints to Accelerate Symbolic Traversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Kavita Ravi, Fabio Somenzi Specification Languages and Methodologies Modeling and Checking Networks of Communicating Real-Time Processes . 265 Jürgen Ruf, Thomas Kropf ”Have I Written Enough Properties?” A Method of Comparison between Specification and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Sagi Katz, Orna Grumberg, Danny Geist Program Slicing of Hardware Description Languages . . . . . . . . . . . . . . . . . . . . 298 E.Clarke, M.Fujita, S.P.Rajan, T.Reps, S.Shankar, T.Teitelbaum Table of

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Correct Hardware Design and Verification Methods

Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.

This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.

http://www.umiacs.umd.edu/~joseph/classes/enee640/fpga-dsp-survey.pdf

Reconfigurable Computing for Digital Signal Processing: A Survey

A system and method for configuring an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. A graphical program is first created, wherein the graphical program implements a measurement function. The graphical program may include a front panel and a block diagram. The method then generates a hardware description based on at least a portion of the graphical program. The hardware description describes a hardware implementation of the at least a portion of the graphical program. The method then configures the programmable hardware element in the instrument utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the at least a portion of the graphical program. The instrument then acquires a signal from an external source, and the programmable hardware element in the instrument executes to perform the measurement function on the signal. The front panel may be used by a user to control the instrument during the measurement.

System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations

For many soft computing methods, we need to generate random numbers to use either as initial estimates or during the learning and search process. Recently, results for evolutionary algorithms, reinforcement learning and neural networks have been reported which indicate that the simultaneous consideration of randomness and opposition is more advantageous than pure randomness. This new scheme, called opposition-based learning, has the apparent effect of accelerating soft computing algorithms. This paper mathematically and also experimentally proves this advantage and, as an application, applies that to accelerate differential evolution (DE). By taking advantage of random numbers and their opposites, the optimization, search or learning process in many soft computing techniques can be accelerated when there is no a priori knowledge about the solution. The mathematical proofs and the results of conducted experiments confirm each other.

Opposition versus randomness in soft computing techniques

In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing.There are two main aspects to the application of formal methods in a design process: the formal framework used to specify desired properties of a design and the verification techniques and tools used to reason about the relationship between a specification and a corresponding implementation. We survey a variety of frameworks and techniques proposed in the literature and applied to actual designs. The specification frameworks we describe include temporal logics, predicate logic, abstraction and refinement, as well as containment between o-regular languages. The verification techniques presented include model checking, automata-theoretic techniques, automated theorem proving, and approaches that integrate the above methods.In order to provide insight into the scope and limitations of currently available techniques, we present a selection of case studies where formal methods were applied to industrial-scale designs, such as microprocessors, floating-point hardware, protocols, memory subsystems, and communications hardware.

Formal verification in hardware design: a survey

Two lightweight block cipher families, Simon and Speck, have been proposed by researchers from the NSA recently. In this paper, we introduce Simeck, a new family of lightweight block ciphers that combines the good design components from both Simon and Speck, in order to devise even more compact and efficient block ciphers. For Simeck32/64, we can achieve 505 GEs (before the Place and Route phase) and 549 GEs (after the Place and Route phase), with the power consumption of 0.417 \(\mu W\) in CMOS 130 nm ASIC, and 454 GEs (before the Place and Route phase) and 488 GEs (after the Place and Route phase), with the power consumption of 1.292 \(\mu W\) in CMOS 65 nm ASIC. Furthermore, all of the instances of Simeck are smaller than the ones of hardware-optimized cipher Simon in terms of area and power consumption in both CMOS 130 nm and CMOS 65 nm techniques. In addition, we also give the security evaluation of Simeck with respect to many traditional cryptanalysis methods, including differential attacks, linear attacks, impossible differential attacks, meet-in-the-middle attacks, and slide attacks. Overall, all of the instances of Simeck can satisfy the area, power, and throughput requirements in passive RFID tags.

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The Simeck Family of Lightweight Block Ciphers

The Forte formal verification environment for datapath-dominated hardware is described. Forte has proven to be effective in large-scale industrial trials and combines an efficient linear-time logic model-checking algorithm, namely the symbolic trajectory evaluation (STE), with lightweight theorem proving in higher-order logic. These are tightly integrated in a general-purpose functional programming language, which both allows the system to be easily customized and at the same time serves as a specification language. The design philosophy behind Forte is presented and the elements of the verification methodology that make it effective in practice are also described.

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An industrially effective environment for formal hardware verification

We describe the use of parametric representations of Boolean predicates to encode data-space constraints and significantly extend the capacity of formal verification. The constraints are used to decompose verifications by sets of case splits and to restrict verifications by validity conditions. Our technique is applicable to any symbolic simulator. We illustrate our technique on state-of-the-art Intel(R) designs, without removing latches or modifying the circuits in any way.

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Formal verification using parametric representations of Boolean constraints

We describe the verification of the IM: a large, complex (12000 gates and 1100 latches) circuit that detects and marks the boundaries between Intel architecture (IA-32) instructions. We verified a gate-level model of the IM against an implementation-independent specification of IA-32 instruction lengths. We used theorem proving to to derive 56 model-checking runs and to verify that the model-checking runs imply that the IM meets the specification for all possible sequences of IA-32 instructions. Our verification discovered eight previously unknown bugs.

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Combining theorem proving and trajectory evaluation in an industrial environment

Floating-point circuits are notoriously difficult to design and verify. For verification, simulation barely offers adequate coverage, conventional model-checking techniques are infeasible, and theorem-proving based verification is not sufficiently mature. In this paper we present the formal verification of a radix-eight, pipelined, IEEE double-precision floating-point multiplier. The verification was carried out using a mixture of model-checking and theorem-proving techniques in the Voss hardware verification system. By combining model-checking and theorem-proving we were able to build on the strengths of both areas and achieve significant results with a reasonable amount of effort.

Mark D. Aagaard

Papers

The Simeck Family of Lightweight Block Ciphers

An industrially effective environment for formal hardware verification

Formal verification using parametric representations of Boolean constraints

Combining theorem proving and trajectory evaluation in an industrial environment

The formal verification of a pipelined double-precision IEEE floating-point multiplier