A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.

System including a fine-grained memory and a less-fine-grained memory

There is provided a semiconductor package and method for fabricating the same. An embodiment of the semiconductor package includes: a semiconductor chip having a first face and a second face, the first face having a plurality of input/output pads formed thereon; a circuit board composed of a resin film having a first face and a second face, a circuit pattern layer including a plurality of bond fingers and ball lands, and a cover coat covering the circuit pattern layer and selectively exposing the plurality of bond fingers and ball lands, the circuit pattern layer being formed on the first face of the resin film, the circuit board having a through hole at the center thereof, the semiconductor chip being placed in the through hole; electrical connection means for electrically connecting the input/output pads of the semiconductor chip to the bond fingers of the circuit board; an encapsulant for encapsulating the semiconductor chip, connection means and a part of the circuit board; and a plurality of conductive balls fused to the circuit board. Accordingly, the semiconductor package becomes very thin and its heat spreading performance is improved.

Semiconductor package and method for fabricating the same

A method for operating a memory (28) that includes a plurality of analog memory cells (32) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is estimated. The estimated CDF is processed so as to compute one or more thresholds. A memory access operation is performed on the cells using the one or more thresholds.

Adaptive Estimation of Memory Cell Read Thresholds

An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.

Reading memory cells using multiple thresholds

A multi-chip memory module comprises multiple standard, surface-mount-type memory chips stacked on top of each other, and a pair of printed circuit boards mounted on opposite sides of the memory chips to electrically interconnect the memory chips. Each printed circuit board has vias that are positioned to form multiple rows, with each row of vias used to connect the printed circuit board to a respective memory chip. The vias falling along the bottom-most row of each printed circuit board are also exposed and are used to surface mount the multi-chip module to pads of a memory board.

Apparatus for stacking semiconductor chips

A data preservation system for flash memory systems with a host system, the flash memory system receiving a host system power supply and energizing an auxiliary energy store therewith and communicating with the host system via an interface bus, wherein, upon loss of the host system power supply, the flash memory system actively isolates the connection to the host system power supply and isolates the interface bus and employs the supplemental energy store to continue write operations to flash memory.

Solid-state memory device with protection against power failure

System and method for preventing data corruption in solid-state memory devices after a power failure

A communications card provides an electronic interface between a host computer and a transmission media line. The communications card includes a releasable adaptor which interconnects an electrical connector of the transmission media line to the communications card when in use. In a first attachment position, which may be used as a storage position, the adaptor integrates into the overall configuration of the communication card to present a configuration that conforms with PCMCIA communication card architecture. For certain PCMCIA socket configurations, this integrated attachment position may also be used as an operational position. In a second attachment position, the adaptor forms an extension of the communications card, extending away from the computer socket to accommodate more restrictive socket configurations. The communications card also includes an optional connector terminal to permit connection to an electrical media line connector of a second type.

Mark Moshayedi

Papers

Apparatus for stacking semiconductor chips

Solid-state memory device with protection against power failure

System and method for preventing data corruption in solid-state memory devices after a power failure

Communications card with integral transmission media line adaptor

Protection against data corruption due to power failure in solid-state memory device