Showing papers by "Marko Hännikäinen published in 2005"

A survey of application distribution in wireless sensor networks

Abstract: Wireless sensor networks (WSNs) are deployed to an area of interest to sense phenomena, process sensed data, and take actions accordingly. Due to the limited WSN node resources, distributed processing is required for completing application tasks. Proposals implementing distribution services for WSNs are evolving on different levels of generality. In this paper, these solutions are reviewed in order to determine the current status. According to the review, existing distribution technologies for computer networks are not applicable for WSNs. Operating systems (OSs) and middleware architectures for WSNs implement separate services for distribution within the existing constraints but an approach providing a complete distributed environment for applications is absent. In order to implement an efficient and adaptive environment, a middleware should be tightly integrated in the underlying OS. We recommend a framework in which a middleware distributes the application processing to a WSN so that the application lifetime is maximized. OS implements services for application tasks and information gathering as well as control interfaces for the middleware.

Software and hardware prototypes of the IEEE 1588 precision time protocol on wireless LAN

Abstract: IEEE 1588 is a standard for precise clock synchronization for networked measurement and control systems in LAN environment. This paper presents the design and implementation of two IEEE 1588 prototypes for wireless LAN (WLAN). The first one is implemented using a Linux PC platform and a standard IEEE 802.11 WLAN with modifications to the network device driver. The second prototype is implemented using an embedded WLAN development board that implements the synchronization functionality using an embedded processor with programmable logic device (PLD) circuits. The measured results show that 1.1 ns average clock offset can be reached on HW based implementation, while Linux PC network driver enables 660 ns with a standard WLAN. Although WLAN is an extremely difficult environment for the synchronization, the results achieved with the prototype are fully comparable to those achieved with wired LAN implementations

UML 2.0 Profile for Embedded System Design

Abstract: The unified modeling language (UML) 2.0 is emerging in the area of embedded system design. This paper presents a new UML 2.0 profile - called TUT-profile - that introduces a set of stereotypes and design rules for an application, platform, and mapping. The profile classifies different application and platform components, and enables their parameterization. The TUT-profile concentrates on the structure of an application and platform, and utilizes standard UML 2.0 for the behavioral modeling. The application is seen as a set of active classes with an internal behavior. Correspondingly, the platform is seen as a component library with a parameterized presentation in UML 2.0 for each library component.

A parallel MPEG-4 encoder for FPGA based multiprocessor SoC

Abstract: A parallel MPEG-4 simple profile encoder for FPGA based multiprocessor system-on-chip (SoC) is presented. The goal is a computationally scalable framework independent of platform. The scalability is achieved by spatial parallelization where images are divided to horizontal slices. Slice coding tasks are mapped to the multiprocessor consisting of four soft-cores arranged into master-slave configuration. Also, the shared memory model is adopted where large images are stored in shared external memory while small on-chip buffers are used for processing. The interconnections between memories and processors are realized with our HIBI network. Our main contributions are the scalable encoder framework as well as methods for coping with limited memory of FPGA. The current software only implementation processes 6 QCIF frames/s with three encoding slaves. In practice, speed-ups of 1.7 and 2.3 have been measured with two and three slaves, respectively. FPGA utilization of current implementation is 59% requiring 24 207 logic elements on Altera Stratix EP1S40.

Efficient hardware implementation of security processing for IEEE 802.15.4 wireless networks

Abstract: The IEEE 802.15.4 standard defines the medium access control and physical layer for low-rate, low-power wireless personal area networks (WPAN). As a number of WPAN applications require protected communications, the standard defines security procedures. Since the procedures typically consume most processing capacity in the limited 802.15.4 devices, efficient implementations are needed. As a solution, this paper presents a compact and energy-efficient hardware design, supporting all the security suites of the standard. Compared to typical WPAN processors, the presented FPGA prototype and the estimated ASIC implementation offer significantly higher performance and lower energy consumption. The FPGA throughput at the highest security level is 90 Mb/s and the energy consumption is 1/190 of an 8-bit microcontroller and 1/5 of an ARM9. The estimated energy consumption for the equivalent ASIC implementation is 1/10 of the FPGA prototype. In addition to 802.15.4, the hardware design supports all wireless technologies derived from the IEEE 802.11i security specification.

Ultra low energy wireless temperature sensor network implementation

Abstract: Condition monitoring in buildings is one of the most potential and foreseen applications for wireless sensor networks (WSN). This paper presents the design and full scale prototype implementation of WSN for temperature monitoring. The prototypes are implemented using low power commercial of-the-shelf components including a 2.4 GHz radio, microcontrollers, and a custom TUTWSN communication protocol. A user application provides a graphical data analysis. Measurements indicate 183 muW to 390 muW average node power consumptions, as temperature is measured at 5 s intervals and data is multi-hop routed to a gateway. Predicted lifetime with two AA batteries is up to 4.9 years. In addition, experiments indicate that time accuracy is extremely important in hardware prototypes

Design of transport triggered architecture processors for wireless encryption

Abstract: Transport triggered architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In this paper TTA processors for the RC4 and AES encryption algorithms of the new IEEE 802.11i WLAN security standard are designed. Special operations efficiently supporting the ciphers are developed. The TTA design flow is utilized for finding configurations with the best performance-size ratios. The size of the configuration supporting both the algorithms is 69.4 kgates and the throughput 100 Mb/s for RC4 and 68.5 Mb/s for AES at 100 MHz in the 0.13 /spl mu/m CMOS technology. Compared to commercial processors of the same wireless application domain, higher throughputs are achieved at significantly smaller area and lower clock speed, which also results in decreased energy consumption.

Wireless sensor network implementation for industrial linear position metering

Abstract: This paper presents the design and performance measurements of a prototype wireless sensor network (WSN) for industrial linear position metering. Design includes two different prototype platforms and a user application. Prototypes combine energy efficient commercial off-the-shelf components including a 2.4 GHz radio, and the custom TUTWSN communication protocols resulting high robustness, autonomous operation and very low power consumption. The user application displays sensor data graphically and enables further data analysis. Measurements contain component power analysis and prototype performance measurements. The measurements indicate 200 /spl mu/W to 400 /spl mu/W average node power consumption, as 16-bit sample is measured with 1 Hz sample rate, and routed to a WSN gateway with 1 s latency per hop and 512 bps throughput between nodes. Predicted lifetime of implemented WSN is 2 months with a small rechargeable battery or over 2 years with two AA batteries.

Performance Modeling and Reporting for the UML 2.0 Design of Embedded Systems

Abstract: This paper presents a new performance modeling approach for the design of embedded real-time systems using UML 2.0. The approach responds to the lack of specific semantics for the performance modeling. The existing UML metamodel is extended by defining stereotypes to include the message latency and execution time in UML statecharts. The information may contain both the real-time constraints and measured values that are back-annotated to the UML model. Further, fully automated model transformation is used to visualize this information with sequence diagrams. The modeling approach has been prototyped with the UML implementation of a WLAN medium access control protocol. The experiences proved the approach to be practical and intuitive.

Energy optimized beacon transmission rate in a wireless sensor network

Abstract: Resource constrained wireless sensor networks (WSN) require an energy efficient medium access control (MAC) protocol that minimizes the radio active time (duty cycle). Time slotted MAC schemes provide lowest duty cycles by dividing time into consecutive data exchange and sleep periods. Synchronization for data exchange and network maintenance is achieved by exchanging beacons. For detecting changes in network topology, nodes periodically perform scanning during which beacons are received from neighbors. This is energy consuming, and the energy required equals to the transmission of thousands of packets. This paper shows that the energy consumption is mainly depending on the beacon transmission rate, and that an optimal rate is a function of three parameters: a network scanning interval, beacon transmission energy, and radio reception power. The optimal beacon transmission rate is derived for a TUTWSN prototype by power analysis and energy models. According to the analysis, the optimization decreases the average network energy consumption up to an order of magnitude. For the prototype, the optimal beacon transmission rate is 3.7 Hz, when network scanning is performed with 2 minutes intervals

Multihop IEEE 802.11b WLAN Performance for VoIP

Abstract: This paper evaluates the performance of IEEE 802.11b WLAN for supporting multihop voice over IP (VoIP) service. Evaluation is carried out using the NS-2 network simulator and the mean opinion score (MOS) as a criteria for measuring the quality of a VoIP connection. The results show that the mean number of hops between a VoIP transmitter and receiver has the main effect on the number of calls with acceptable quality. On a small network where connections cause interference to each other already three hops cause problems. The mean number of hops can be decreased with a supporting access point (AP) infrastructure. Also the type of interfering traffic affects. The voice quality in VoIP is sensitive to transmission losses, and VoIP cannot compete equally with high data rate applications

High abstraction level design and implementation framework for wireless sensor networks

Abstract: The diversity of applications, scarce resources, and large scale set demanding requirements for Wireless Sensor Networks (WSN). All requirements cannot be fulfilled by a general purpose WSN, but a development of application specific WSNs is needed. We present a novel WIreless SEnsor NEtwork Simulator (WISENES) framework for rapid design, simulation, evaluation, and implementation of both single nodes and large WSNs. New WSN design starts from high level Specification and Description Language (SDL) model, which is simulated and implemented on a prototype through code generation. One of the novel features is the back-annotation of measured values from physical prototypes to SDL model. The scalability and performance of WISENES have been evaluated with TUTWSN that is a very energy efficient new WSN. The results show only 6.7 percent difference between modeled and measured TUTWSN prototype energy consumption. Thus, WISENES hastens the development of WSN protocols and their evaluation in large networks.

A middleware for task allocation in wireless sensor networks

Abstract: Resource constrained platforms, dynamic nature, and complex applications set challenges to the development of wireless sensor networks (WSN). Sophisticated tasking and networking control is required in WSNs to reach lifetimes in order of years. This paper presents a WSN node middleware, which controls task allocation and WSN topology according to the current requirements of the application. The middleware uses a lightweight algorithm that balances communication and computation load between nodes. The discovering of resources and application tasks are comprised by a tuple space that selectively disperses information to nodes. The middleware has been implemented and evaluated in a wireless sensor network simulator (WISENES) that models resource usage and network operation accurately. The results show that in a static network configuration the obtained lifetime with our middleware is 6.8 times longer compared to an uncontrolled network while the increase in processing is negligible and the peek data memory usage increases by 11.6%. In a dynamically changing network the lifetime increases by a factor 3.9. Our middleware does not limit the applications and networks and improves the performance and predictability of WSNs significantly

Design and implementation of an enhanced security layer for Bluetooth

Abstract: This paper proposes a new Enhanced Security Layer (ESL) for Bluetooth. The security level is increased by replacing the encryption with AES and adding in- tegrity protection. As ESL is placed on the top of the standard controller interface, it can be integrated into any Bluetooth implementation. A prototype implementation of ESL is presented. The security processing is implemented in hardware for high performance. The design consumes fewer resources and has higher throughput (214 Mb/s) than the standard design. The programming interface supports straightforward application development.

Design and implementation of a WLAN terminal using UML 2.0 based design flow

Abstract: This paper presents a UML 2.0 based design flow for real-time embedded systems. The flow starts with UML 2.0 application, architecture and mapping models for our TUTWLAN terminal with its medium access control protocol. As a result, the hardware/software implementation on Altera Excalibur FPGA is achieved. Implementation utilizes eCos real-time operating system, and hardware accelerators for time-critical protocol functions. The design flow is prototyped in practice showing rapid UML 2.0 application model modification, real-time protocol processing in an image transfer application, and execution monitoring.

Frequency management tool for multi-cell WLAN performance optimization

Abstract: Careful configuration of frequencies for WLAN access points (AP) is crucial for ensuring the optimal performance of the network. Thus, advanced tools for WLAN frequency management tasks are needed. This paper presents a practical tool for the frequency management in IEEE 802.11 WLANs. The tool minimizes the interference between APs and consequently maximizes the effective capacity of the network. It also contains a graphical user interface (GUI) showing an illustrative view of the network state in frequency domain. The tool has been designed for administrators of medium and large WLAN networks, such as used in companies, airports, and campus areas. In the presented case, the throughput of the optimized network was 60 % higher compared to the original network with random channels

Acceleration of Modular Exponentiation on System-on-a-Programmable-Chip

Abstract: Computing modular exponentiations with long integers is required in a number of security protocols Since security procedures typically consume large amount of processing capacity in network devices, efficient implementations are needed As a solution, this paper presents an exponentiation accelerator suited for efficient processing in security protocols using public key schemes, such as TLS and IPsec The accelerator is implemented on a system-on-a-programmable-chip, partitioned into software control and hardware processing Compared to previous radix-2 designs, significantly higher performance is achieved The design computes a full exponentiation in (n+k)(n+4) clock cycles, in which n is the bit length of the modulus and the exponent and k is the number of ones in the binary representation of the exponent In the average case, the design executes the exponentiation 25% faster than the previous hardware designs at equal clock speeds The proposed exponentiation control and 1-cycle processing mode can also be utilized for improving higher radix designs

Interfacing UML 2.0 for Multiprocessor System-on-Chip Design Flow

Abstract: UML 20 can be extended for embedded system design Our solution is a well-defined modeling approach, known as TUT-profile, for UML 20 together with our system-on-chip architecture exploration tools The two major novel features are an explicit control of real-time constraints at UML level and the transformation of the original UML model using back-annotated results of SoC architecture exploration In this way, all information is kept up to date in a single UML model, in contrary to other flows that use UML only as a front end This paper focuses on the interface between UML model and the architecture exploration and presents conversions, tools, and intermediate format required for the flow

Co-simulation ofWireless Local Area Network Terminals with Protocol Software Implemented in SDL

Abstract: This paper presents the verification of our WLAN terminal (TUTWLAN), with its medium access control protocol and test applications, using cycle-accurate hardware/ software co-simulation. The protocol software has been implemented using SDL and automatic C code generation. The hardware implementation of the terminal contains hardware accelerators for time-critical protocol functions. Full system co-simulations were used for both the functional verification and performance evaluation of a single TUTWLAN terminal as well as a network of terminals. With simulations, the performance bottlenecks were identified, and the results enable the implementing of the next generation TUTWLAN terminal as a single-chip.