In a system for compressing video data, the degree of global motion between a plurality of successive frames is determined for use in designating and spacing reference frames, relative to the global motion exceeding predetermined thresholds or levels of motion between certain ones of the frames.

Method and apparatus for video data compression using temporally adaptive motion interpolation

An encoder segments frames in a sequence of digital images into multiple regions of arbitrary shape each of which has a corresponding motion vector relative to a previous decoded frame. A hierarchical multi-resolution motion estimation and segmentation technique, which segments the frame into multiple blocks and which assigns a best motion vector to each block is used. Blocks having the same or similar motion vector are then merged to form the arbitrarily-shaped regions. The shape of each region is coded, and a decision is made to code additional image data of each region in one of three modes. In a first inter-frame mode, a motion vector associated with a region is encoded. In a second inter-frame mode, a prediction error for the region is also encoded. In an intra-frame mode, the intensity of each picture element in the region is encoded. A region interior coder with frequency domain region-zeroing and space domain region-enforcing operations is employed for effectively coding the interior image data of the arbitrarily-shaped regions. The region interior coder uses an iterative technique based on the theory of successive projection onto convex sets (POCS) to find the best values for a group of selected transform coefficients. The coded information, including the shape of the region, the choice of the mode, and the motion vector and/or the region's interior image data, may then be transmitted to a decoder where the image can be reconstructed.

Method and apparatus for a region-based approach to coding a sequence of video images

The real-time image recording/reproducing apparatus of this invention includes: image input means (2) for receiving an image signal; compression means (4) for compressing the image signal so as to produce compressed data; storing means (3) for storing the compressed data; control means (1) for judging whether or not a sufficient empty space required for storing the compressed data exists in the storing means (3), and storing the compressed data in the storing means (3) if a sufficient empty space exists, or allocating a required empty space by releasing oldest data among the compressed data stored in the storing means (3) and storing the compressed data in the allocated empty space if a sufficient empty space does not exist; instruction input means (5) for receiving replay instruction; expansion means (4) for expanding the compressed data stored in the storing means (3) in response to the replay instruction input from the instruction input means (5) so as to produce image data; and output means (6-8) for outputting the image data.

Real-time image recording/producing method and apparatus and video library system

In this paper, we describe a fully pipelined single chip VLSI architecture for implementing the JPEG baseline image compression standard. The architecture exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The architecture for discrete cosine transform and the entropy encoder are based on efficient algorithms designed for high speed VLSI implementation. The entire architecture can be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024/spl times/1024 color images. >

JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard

A unified approach to the realization of forward and inverse discrete cosine transforms is proposed. With this approach, an odd prime length DCT/IDCT with two half-length convolutions can be realized without extra overhead in terms of the number of multiplications. The formulation is most suitable for realization using distributed arithmetic, in which case typical convolvers can be used as the core unit for the hardware implementation of the transforms. Hence, an efficient unified DCT/IDCT chip is proposed to demonstrate the superiority of the formulation. The proposed architecture can easily meet the speed requirement of 14.3 MHz real-time operation with the current 2 mu m CMOS technology. >

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On the realization of discrete cosine transform using the distributed arithmetic

In a moving image encoding apparatus, an image signal is converted into a digital image signal by an A/D converter and is stored in frame memory 110 In addition, a movement vector detector 300 detects a movement of the output of the frame memory 110 In an orthogonal transformer 130, a difference signal between a present frame image which is stored in the frame memory 110 and a previous frame image which is stored in a variable delay frame memory 210 is supplied, in which the difference signal is converted by orthogonal transformation The orthogonally transformed transformation signal is quantized into a linear or nonlinear discrete level on the basis of a step width of quantization from a step size controller 600 in a quantizer 140 Then, the quantized data is encoded into a variable length code in a variable length encoder 150 A movement vector detector 300 detects movement of the image by pattern matching processing between the present frame and the previous frame A movement vector/encoding mode judger 310 generates the movement vector 3 and the encoding mode 4 The variable length code is transmitted to the transmission circuit after adding a movement vector 3 and encoding mode 4 In these operations, a frame rate controller 700 controls the processing rate of each frame image in the entire apparatus Frame rate controller 700 calculates a total frame skip number S T which corresponds to the total number of frames that are not transmitted after a frame has been transmitted The total frame skip number S T is calculated by selecting a smaller sum of an externally set signal S min , signal S M which is calculated from the degree of movement compensation and S S which is calculated from the degree of quantization, and an externally set signal S max 

Frame skip encoding apparatus for moving images

A motion vector detecting apparatus for detecting motion vectors based on a current frame data and the preceding frame data In the motion vector detecting apparatus, first and second memories are provided in order to store the current frame data and the preceding frame data Additionally, a number of first cache memories, a number of second cache memories, a control circuit, and a motion vector calculation circuit are provided The control circuit selects the input cache memories into which pixel data are to be written, and the output cache memories, from which pixel data are to be read out, from the first and second cache memories, so that the input cache memories and the output cache memories have no redundant cache memory Pixel data corresponding to the detection image blocks stored in the first memory and pixel data corresponding to the search image blocks stored in the second memory are sequentially written in the selected input cache memories of the first and second cache memories Simultaneously, the pixel data corresponding to the detection image blocks and the search image blocks are sequentially read out from the selected output cache memories, and are sequentially supplied to the motion vector calculation circuit

Motion vector detecting apparatus for video telephone/teleconference systems

An image signal encoding apparatus having a control means for detecting a degree of redundancy of an inputted image signal and for conducting frame skip control based on a frame skip number determination and a determined skip number, an encoding processing means for processing a frame signal indicated by a transmission from said control means by block units into which a screen is divided, quantizing this signal, and encoding and outputting this signal through the medium of a transmission buffer, and a step size control means for controlling the step size of the quantization, characterized in that the step size control means comprises a correction buffer amount calculation means, which calculates a correction buffer amount indicating an excess in the transmission buffer from the frame skip number and a previously supplied transmission speed, and a step size calculation means, which outputs a quantization step size which is smaller as the correction buffer amount indicates a larger excess of the transmission buffer.

Image signal encoding apparatus and method for controlling quantization step size in accordance with frame skip numbers

The Discrete Cosine Transform (DCT) is considered to be the most effective transfonn coding technique for image and video compression. In this paper a new implementation of an experimental prototype multi-function DCT/IDCT (Inverse DCT) chip is reported. The chip is based on a distributed arithmetic architecture. The main features of the chip include: 1) The DCT and the IDCT are integrated in the same chip 2) the chip achieves high accuracy exceeding the stringent requirements of a proposed CCITF standard 3) it achieves a high operating speed of 27 MHz and is thus applicable to a wide-range of real-time image and video applications 4) the internal clock frequency is the same as the pixel rate and 5) with an on-chip zigzag scan converter and an adder/subtractor it is multifunctional and useful in a DPCM configuration. The chip is implemented with standard cells and contains about 156k transistors.© (1990) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

VLSI architecture and implementation of a multifunction, forward/inverse discrete cosine transform processor

PURPOSE:To attain the retrieval at an expanded retrieval range by specifying the relation between number P of arithmetic sections having a retrieval range of a size of (2M-1)X(2M-1) picture elements and number Q of arithmetic sections having a retrieval range of a size of (QXM-1)X(QXM-1) picture elements. CONSTITUTION:The detector consists of four arithmetic sections 101 -104 and an external comparator section 200, and when the size of detection block is selected to be, each of the arithmetic sections 101-104 is a circuit having a retrieval range of (2M-1)X(2M-1). Then the size of a detection block is selected as MXM picture elements and the size at expansion is selected as (QXM-1)X(QXM-1) and number of the arithmetic section is P, then the relation between the number P and the expansion ratio Q is set to equation I, in this case Q>2 exists. Thus, plural same arithmetic sections are used to expand the retrieval range of a moving vector.

Maruyama Masanori

Papers

Frame skip encoding apparatus for moving images

Motion vector detecting apparatus for video telephone/teleconference systems

Image signal encoding apparatus and method for controlling quantization step size in accordance with frame skip numbers

VLSI architecture and implementation of a multifunction, forward/inverse discrete cosine transform processor

Moving vector detector