Recent directions in netlist partitioning: a survey

A method of automatically placing transistors of a folded transistor circuit for synthesizing rows of transistors in a semiconductor layout (172). First, an initial placement of transistors is generated (802). Next, a candidate move of transistors is selected (804). Then the change in cost of the placement resulting from applying the candidate move is evaluated (806). A decision is made to accept the candidate move based on the evaluation of its cost (808). If accepted, the move is performed (810) and the cost of the placement is updated (812). Finally, a decision to terminate the process is made (814).

Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Method for design optimization using logical and physical information

An automated logic circuit design system uses a common database to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions. In this way, the need to translate circuit descriptions between tools is eliminated, thus leading to increased speed, flexibility and integration. The common database includes entities, models, cells, pins, busses and nets. The data-flow graphs are stored as graphs, the nodes in a graph as cells, and the edges as busses. Physical design data is available by storing the cells in a model in a KD tree. This allows queries on cells in the netlist located in the layout within arbitrary areas.

Method for storing multiple levels of design data in a common database

A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.

Advanced modular cell placement system

To reduce a circuit block in area, the present invention provides an LSI layout design method having a cell changing processing for reducing a pure wiring zone in area. By an input processing, circuit design information and cell library are entered. Then, a layout of cells arranged in a plurality of cell rows is designed by a cell placing processing. Then, the height of a wiring zone required between cell rows is estimated by a wiring zone height estimating processing. To reduce the area of a pure wiring zone other than the over-the-cell wiring zones, each of placed cells is changed, by a cell changing processing, to a cell having the same specifications and a different shape or a different terminal position. A layout of cell interconnection is designed by a wiring processing. Based on the layout thus obtained by the processings above-mentioned, a mask pattern is prepared and supplied by a mask pattern preparing processing.

Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones

The Monte Carlo simulations based on the 'heat bath' algorithms are implemented for the following classical spin systems: (i) the continuous-spin Ising model; (ii) the XY model and (iii) the Heisenberg model.

https://iopscience.iop.org/article/10.1088/0022-3719/19/14/020/pdf

On the implementation of the heat bath algorithms for Monte Carlo simulations of classical Heisenberg spin systems

There is provided a placement optimization system for determining layout in printed circuits and semiconductor substrates, comprising input means for inputting circuit connection information, placement optimization means for deriving wiring density distribution on the basis of the circuit connection information, evaluating the height and/or width of the wiring region statistically estimated from the wiring density distribution, and output means for outputting the resultant placement position information. Further, the placement optimization system may comprise means for collecting placement elements into sets, determining placement of the sets, then developing the sets into elements, and determining optimum placement positions of the elements.

Placement optimization system aided by CAD

During an optimization of an organization of mutually-related elements, an element organization is gradually changed toward an objective specification by local changes of the element organization. A value of an objective function depends on a degree of a nearness of the element organization to the objective specification. A redundancy function of a number of elements in an improvement group is determined in consideration of a fluctuation in the value of the objective function, so that suitable changes of the improvement group are performed by use of the definite redundancy. An intermediate element organization is rejected and accepted in accordance with the redundancy function value, so that a final element organization can be obtained in consideration of a global aspect of the element organization.

System for optimizing a physical organization of elements of an integrated circuit chip through the convergence of a redundancy function

A plurality of wires are effectively laid in a channel having a plurality of wiring layers and sandwiched between two rows of terminals. In order to complete channel routing, horizontal segments of the wires are initially generated. The horizontal segments are then allocated on at least one imaginary segment generated on each layer contained in the channel. The imaginary segment is in parallel with the rows of terminals in the channel. The horizontal segments are bent for reduction of the channel height based on design rules for each layer. Finally, vertical segments of the wires are generated.

Masahiko Toyonaga

Papers

Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones

On the implementation of the heat bath algorithms for Monte Carlo simulations of classical Heisenberg spin systems

Placement optimization system aided by CAD

System for optimizing a physical organization of elements of an integrated circuit chip through the convergence of a redundancy function

Channel routing method