A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single processor and instruction set. Advantageously, the embedded logic on the DRAM chip implements the memory intensive processing tasks, thus reducing the amount of traffic that needs to be bussed back and forth between the CPU core and the embedded DRAM chips. The embedded DRAM logic monitors and manipulates the instruction stream into the CPU core. The architecture of the instruction set, data paths, addressing, control, caching, and interfaces are developed to allow the system to operate using a standard programming model. Specialized video and graphics processing systems are developed. Also, an extended very long instruction word (VLIW) architecture implemented as a primary VLIW processor coupled to an embedded DRAM VLIW extension processor efficiently deals with memory intensive tasks. In different embodiments, standard software can be accelerated either with or without the express knowledge of the processor.

Split embedded DRAM processor

The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch prediction cache (BPC) includes a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address. A separate instruction cache is provided for normal execution of instructions, and all of the instructions written into the branch prediction cache from the system bus must also be stored in the instruction cache. The instruction cache monitors the system bus for attempts to write to the address of an instruction contained in the instruction cache. Upon such a detection, that entry in the instruction cache is invalidated, and the corresponding entry in the branch prediction cache is invalidated. A subsequent attempt to use an instruction in the branch prediction cache which has been invalidated will detect that it is not valid, and will instead go to main memory to fetch the instruction, where it has been modified.

Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

High performance, superscalar-based computer system with out-of-order instruction execution

A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address of the instruction block's successor and information indicating the location of a branch instruction within the instruction block. Thus, the next cache block can be easily fetched without waiting on a decoder or execution unit to indicate the proper fetch action to be taken for correctly predicted branching.

System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache

An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.

Two-level branch prediction cache

A data processor comprises an instruction decode unit (119) for receiving operation codes from an instruction memory (103) A second decoder (114) of the instruction decode unit (119) decodes an operation code for a multiply-add operation, and a second operation unit (117) receives 2 data stored in a register file (115) to perform the multiply-add operation In parallel with the operations of the second decoder (114) and the second operation unit (117), a first decoder (113) of the instruction decode unit (119) decodes an operation code for 2 data load, and an operand access unit (104) causes 2 data (eg, n bits each) stored in an internal data memory (105) to be transferred in parallel in the form of combined 2n-bit data to a first operation unit (116) Then, two predetermined registers of the register file (115) store the respective n-bit data from the first operation unit (116)

Data processor and method of processing data

A branch prediction for predicting, prior to executing a given branch instruction, whether the branch condition of the given branch instruction will be established, utilizes an address of an instruction that precedes the given branch instruction to access the branch prediction information for the given branch instruction from a branch prediction table.

Preceding instruction address based branch prediction in a pipelined processor

A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

Pipeline processor, with return address stack storing only pre-return processed addresses for judging validity and correction of unprocessed address

A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

Data processor calculating branch target address of a branch instruction in parallel with decoding of the instruction

Pipelining of instruction execution significantly improves computer performance, but high dependencies between instructions limit the maximum concurrency that is achievable by pipelining. A hardware scheme to avoid pipeline interlock delays caused by dependencies in address generation is proposed. This scheme is implemented in the 32-b microprocessor M32/100. The M32/100 has a hardware interlock mechanism with scoreboard registers and a working stack pointer that is modified prior to the execution of each instruction. A simulator has been written and several benchmarks have been executed to investigate the performance achieved by these schemes. >

Masahito Matsuo

Papers

Data processor and method of processing data

Preceding instruction address based branch prediction in a pipelined processor

Pipeline processor, with return address stack storing only pre-return processed addresses for judging validity and correction of unprocessed address

Data processor calculating branch target address of a branch instruction in parallel with decoding of the instruction

A strategy for avoiding pipeline interlock delays in a microprocessor