An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface Hydrogen is introduced into The active layer A thin film comprising SiO x N y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO x N y  Also, a thin film comprising SiO x N y is formed under the active layer The active layer includes a metal element at a concentration of 1×10 15 to 1×10 19 cm −3 and hydrogen at a concentration of 2×10 19 to 5×10 21 cm −3 

Semiconductor device and method for forming the same

A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

High-breakdown-voltage semiconductor device

At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.

Method of Manufacturing a Semiconductor Device

A process for fabricating a thin film transistor, which comprises crystallizing an amorphous silicon film, forming thereon a gate insulating film and a gate electrode, implanting impurities in a self-aligned manner, adhering a coating containing a catalyst element which accelerates the crystallization of the silicon film, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities. Otherwise, the catalyst element can be incorporated into the structure by introducing it into the impurity region by means of ion implantation and the like. Also a process for fabricating a thin film transistor, which comprises forming a gate electrode, a gate insulating film, and an amorphous silicon film on a substrate, implanting impurities into the amorphous silicon film to form source and drain regions as the impurity regions, introducing a catalyst element into the impurity region by adhering a coating containing the catalyst element of by means of ion doping and the like, and annealing the resulting structure at a temperature lower than the deformation temperature of the substrate to activate the doped impurities.

Transistor and process for fabricating the same

A semiconductor substrate has a power region and a control region. The control region is located in the center portion of the substrate, and the power region surrounds the control region and is separated therefrom. A vertical type, MOS transistor, i.e., an active semiconductor element, is formed on the power region. An insulation film is formed on part of the control region. A polycrystalline silicon diode, which functions as a heat-sensitive element, is formed on the insulation film. A control section comprising a lateral type, MOS transistor is also formed on the control region. The lateral type, MOS transistor is connected to receive a signal form the polycrystalline silicon diode. Further, a polycrystalline silicon resistor, which determines a circuit constant, is formed on the insulation film. The MOS transistor protects the active semiconductor element in response to a signal supplied from the heat-sensitive element showing that the temperature of the semiconductor substrate has risen above a predetermined value. For example, the active semiconductor element may be disabled until the detected temperature drops below a predetermined value.

Semiconductor device with protective means against overheating

A method for manufacturing a DMOS which comprises forming a first conductive type layer on a substrate, forming a gate oxide layer thereon, forming a gate electrode layer and a second insulating layer successively on the gate oxide layer, forming a second conductive type body region and a first conductive type source region having a narrower width by implanting impurities utilizing the second insulating layer as a mask, forming a side wall spacer of an insulating material on at least a side portion of the gate electrode, forming a conductive passage penetrating the source region and extending into the body region while utilizing the second insulating layer and the side wall spacer as mask, optionally implanting the exposed body region, further excessively etching the sidewall spacer, the masking layer overlying the gate, and the gate oxide prior to providing an electrode connecting the source and body regions.

Method of manufacturing a DMOS

PURPOSE:To prevent punch through between a source and drain, to obtain an arbitrary avalanche breakdown voltage and to provide a low ON-resistance vertical MOS transistor, by uniformly flowing a breakdown current through the bottom part of a second-conductivity type diffused layer when a high reverse voltage such as a surge voltage is applied. CONSTITUTION:A drain region has a conventional three-layer structure. A P-type diffused layer 5 is formed in an N type low concentration layer 4. The bottom part T of the layer 5 reaches an N-type medium concentration layer 3. The acceptor impurity concentration of the layer can be variously adjusted in a range, which is higher than the impurity concentration of a P-type well region 6. Then, the region 6, which has the acceptor impurity concentration determined by the desired threshold voltage value of a vertical MOS transistor, is formed in the layers 5 and 4. An N type source region 7, which has donor impurity concentration, is formed in the layer 5 and the region 6. Then a gate oxide film 8 is formed at a part on each of the layers 4 and 5 and the regions 6 and 7. A gate electrode layer 9 and an interlayer insulating film 10 are sequentially formed thereon. A source electrode 11 is formed on the entire surface. The withstanding voltage of the P-N junction at each place in such a vertical MOS transistor becomes the minimum at the bottom part T of the layer 5. Breakdown starts at this part, and its current flows uniformly through the bottom part T.

Vertical mos transistor

A diode which includes a first region formed in a polycrystalline silicon layer formed on a substrate. The diode has a predetermined width W and is one of an intrinsic region and a region including impurities at a low concentration therein, a second region and a third region including P-type impurities and N-type impurities therein respectively and both being oppositely arranged from each other with the first region therebetween in the polycrystalline silicon layer. Electrodes are electrically connected to the second region and the third region respectively, and further the film characteristic of the polycrystalline silicon layer and the predetermined width W thereof are determined in such a manner as to fulfill the following equation: W.sub.D ≦W≦L L represents a carrier diffusion length and W D represents a width of the depletion layer created in the polycrystalline silicon layer when the voltage corresponding to the withstand voltage required by the polycrystalline diode as mentioned above, is applied thereto.

Method for making a polycrystalline diode having high breakdown

A power MOS transistor and a current sensing MOS transistor have a common drain electrode connected to a load. The gates of these MOS transistors are commonly controlled in response to an input control signal. A load current sensing resistor element is connected between the source electrodes of these transistors. A voltage signal sensed by the load sensing resistor element is amplified by a differential amplifier constituted by a pair of depletion type MOS transistors. The amplified output controls the MOS transistors, and the MOS transistors variably control a voltage of the input control signal to be supplied to the power and current sensing MOS transistors. The power MOS transistor, the current sensing MOS transistor, the depletion MOS transistor, the current control MOS transistor, and the like have the same conductivity type.

Masami Yamaoka

Papers

Semiconductor device with protective means against overheating

Method of manufacturing a DMOS

Vertical mos transistor

Method for making a polycrystalline diode having high breakdown

Power semiconductor apparatus