An analog to digital converter is provided in which the outputs of first and second digital to analog converters DACl and DAC2 are combined in a combining circuit so as to form a plurality of decision thresholds. This enables two or more bits to be determined in a single trial.

Analog-to-digital converter

A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate (42) and the bit line (46) during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer (42) to the control gate (38). The cell is adapted so that the source (32) for each cell within the array in the source of an adjacent cell and the drain (34) is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate (104) through openings in a first insulator (106) that is preferably the field oxide. A second insulator (112) is deposited over the first insulator (106) over the substrate (104) and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer (114). The field oxide (106) is selectively removed. A gate oxide (118) is grown and a second polysilicon layer is formed and then etched to form spacers (124) along the edges of the first polysilicon (114) second insulator structure (112). The second polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A third polysilicon layer (38) is formed over the tunneling insulator.

Spacer flash cell process

An analog-to-digital (A/D) converter capable of receiving a differential input for improved noise rejection and having two static resistive ladders for reducing power consumption. The resistive ladders are anti-parallel and have a high impedance, each dividing fixed voltages into a group of reference voltages. A first stage of comparators compares the positive signal of the differential input with each of the reference voltages from one of the resistive ladder, and the negative input signal with each of the reference voltages from the other resistive ladder. The outputs of the first stage of comparators are compared by a second stage of comparators to generate a group of binary outputs in parallel. An encoder converts the outputs of the second-stage comparators into a digital value. Decoupling capacitors are also provided to reduce the AC impedance of the resistive ladders.

Differential analog-to-digital converter with low power consumption

There is provided an A/D converter that outputs a digital output signal obtained by digitalizing an analog input signal. The A/D converter includes a bit selecting section that selects a conversion object bit from a high-order bit to a low-order bit of the digital output signal in order, a threshold-value controlling section that determines a threshold data expressing a boundary value between zero and one of the conversion object bit, a D/A converting section that digital-to-analog converts the threshold data and generates an analog threshold value, a comparing section that compares, at a plurality of different timings in a conversion time interval determining a value of the conversion object bit, the analog input signal and the analog threshold value and outputs a plurality of comparison results at the timings, and a bit determining section that determines the value of the conversion object bit.

A-D converter and A-D convert method

A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed. A gate oxide is grown and a second polysilicon layer is formed and then etched to form spacers along the edges of the first polysilicon/second insulator structure. The second polysilicon is selectively etched and a tunneling insulator layer is formed thereover. A third polysilicon layer is formed over the tunneling insulator.

Spacer flash cell device with vertically oriented floating gate

A serial-to-parallel type A/D converter includes a resistance array, a plurality of comparators for upper bits, a plurality of comparators for lower bits, an encoder for upper bits, an encoder for lower bits and an adder. The resistance array divides a predetermined reference voltage to generate upper reference voltages, and by dividing the step width of the upper reference voltage, generates lower reference voltages. The plurality of comparators for the upper bits compare the analog input signal with the upper reference voltages, and applies the result of comparison to the encoder for the upper bits. The encoder for the upper bits calculates an estimated value of the upper bits based on the result of comparison, and select second reference voltages in the range provided by adding ±1/2 LSB to 1LSB corresponding to the estimated value of the upper bits. The plurality of comparators for the lower bits calculate the lower bits and a correcting bit based on the selected second reference voltages. The adder adds the correcting bit to the estimated value of the upper bits to correct the estimated value.

Masashi Yonemaru

Papers

Serial-to-parallel type analog-digital converting apparatus and operating method thereof