An electrical conductive path for medical electronic device generally includes a plurality of stackable molded non-conductive housing with each housing having a bore therethrough alignable with adjacent housing bores. The adjacent housings and define any combination when stacked, spaced apart slots for receiving a plurality of electrically conductive spring rings. A plurality of electrically conducting garter springs are disposed within corresponding spring rings and a cable is provided including wires attached to corresponding spring rings.

Electrical conductive path for a medical electronics device

This invention is an iterative technique for division. The divisor has N bits and the numerator has more than N bits, generally 2N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator in left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations of the division is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. If this is nonzero, then the numerator shifts this number of places and the corresponding quotient bits are set to "0". Next the division technique calculates the difference between the N most significant bits of the numerator and the divisor. If the difference is greater than or equal to zero, then the next quotient bit is "1". If the difference is less than zero, then the next quotient bit is "0". The difference is substituted for the N most significant bits of the numerator, if this difference was greater than or equal to zero. Then the numerator is left shifted one place. These iterations repeat until the number of iterations exceeds N. Then the quotient is completely formed and the data of the last numerator is the remainder of the division. This technique eliminates useless data manipulation for the cases where this technique determines the quotient bits are "0". Using pre- and post-processing this technique can be used with signed numbers. In the preferred embodiment of this invention, the division logic is embodied in at least one digital image/graphics processor as a part of a multiprocessor formed in a single integrated circuit used in image processing.

Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive OR

A dividend or partial remainder is stored in a partial remainder register. An output of the partial remainder register is shifted to the left by a radix which uses the power of 2 and is larger than 2. A divisor is stored in a divisor register. Comparison constants obtained by subjecting an output of the divisor register to predetermined operations are stored in comparison constant registers. Subtracters respectively receive outputs of the comparison constant registers as one input, receive upper bits of a bit number representing a precision required for conversion and included in the output of the partial remainder shifter as another input, and compare the magnitudes of the two inputs with each other to derive partial quotients. A selector shifts and selects an output of the divisor register according to the signs of the remainder quotients output from the subtracters to create a factor having a value equal to the integer multiple of the divisor. An adder/subtracter receives an output of the selector and an output of the partial remainder shifter and the addition or subtraction of the adder/subtracter is selectively specified by the sign bit of an output of the partial remainder shifter to derive a partial remainder.

High-radix divider

In response to an error signal from a source of an MPEG audio data stream, a decoder replaces data with an error code and temporarily enables error handling. The error code is a valid bit combination rarely found in MPEG audio data frames. During audio decoding with error handling enabled, the decoder checks for the error code and replaces the error code with reconstructed data. Typically, some subband data are replaced with zeros so that an error only changes some of the frequency components.

Error handling process for MPEG decoder

An iterative division technique which forms plural quotient bits per iteration. A data processing apparatus (1100) includes a first register (1101) storing the divisor, a second register initially storing the numerator (1103), a plurality of full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) and an equal number of negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128), and a loop counter (1131). Initially the full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) compute each integral product of the divisor not a power of 2 between 1 and 2 M -1 inclusive, where M is the number of quotient bits to be computed. These factors are stored in latches (1144, 1146, 1147, 1148). The full adders (1112, 1113, 1114, 1115, 1116, 1117, 1118) next subtract in parallel each integral product of the divisor between 1 and 2 M -1 inclusive from the most significant bits of the numerator. Negative detectors (1122, 1123, 1124, 1125, 1126, 1127, 1128) connected to each full adder (1112, 1113, 1114, 1115, 1116, 1117, 1118) indicate the first non-negative difference, which determines plural bits of the quotient and a partial remainder. This process is repeated with partial remainder left shifted M places employed as the numerator a number of iterations based upon the size of the numbers employed and the number of bits per iteration. For signed division the sign of the quotient is set as the exclusive OR of the detected (1102, 1104) respective signs of the numerator and the divisor.

Iterative division apparatus, system and method forming plural quotient bits per iteration

In a divider for dividing a dividend by a divisor to calculate a quotient and a remainder, the divisor being a natural number which is a constant, each of the dividend, the quotient, and the remainder being an integer which is not less than zero, first through N-th comparing circuits compare the dividend with first through N-th predetermined constants. An n-th predetermined constant is equal to n times as large as the divisor, where n is variable between 1 and N, both inclusive. The first through the N-th comparing circuit produce first through N-th comparison result signals. A decoder decodes a combination of the first through the N-th comparison result signals into first and second partial decoded signals. The first partial decoded signal is equal to the quotient. The second partial decoded signal is equal to lower bits of a product of the quotient and the divisor. A subtracter subtracts the second partial decoded signal from lower bits of the dividend to produce the remainder.

Masayuki Kaneda

Papers

Fast divider for a constant divisor