Showing papers by "Massoud Pedram published in 1990"

Floorplanning with pin assignment

Abstract: A hierarchical technique is presented for floorplanning and pin assignment of general cell layouts. Given a set of cells with their shape lists, a layout aspect ratio, relative positions of the external I/O pads and upper bound delay constraints for a set of critical nets, the authors determine shapes and positions of the cells, locations of the floating pins on cells and a global routing solution such that a linear combination of the layout area, the total interconnection length and constraint violations for critical nets is minimized. Floorplanning, pin assignment and global routing influence one another during the hierarchical steps of the algorithm. The pin assignment algorithm is flexible and allows various user specified constraints such as pre-specified pin locations, feedthrough pins, length-critical nets and planar net topologies. Placement, timing and floorplanning results for a Xerox general cell benchmark are reported. >

Timing-driven placement for general cell layout

Abstract: A hierarchical technique is presented for the timing-driven placement of the general cells. It is assumed that maximum interconnection delays for nets are given. These timing constraints are transformed to net length constraints using technology-and process-dependent parameters, circuit-specific data such as input capacitance and output drivability, and the structural description, of the circuit. The problem is divided into a bottom-up clustering phase and a top-down enumerative placement phase. Both the natural connectivities and the net length constraints are considered during the bottom-up phase in order to generate a hierarchical cluster tree. During the top-down placement phase, they place each node of the cluster tree so that the layout area and total interconnection length are minimized while satisfying the net length constraints. >

A hierarchical floorplanning approach

Abstract: A hierarchical floorplanner for general cell layout that exploits accurate shape functions that describe constraints on the leaf cells in order to produce good floorplans is presented. The leaf cells may have highly constrained shapes, or more flexible shapes. The floorplanner trades off the locations, sizes shapes, and pin positions of the cell against each other in order to minimize the layout area and the amount of interconnections. To the extent that the shape functions are accurate, there is no need for design iterations. By imposing a hierarchy in the form of a multiwave cluster tree, the number of floorplanning options is restricted and the problem is simplified by allowing the floorplanner to operate on one hierarchical cell at a time. The shape functions and the hierarchical approach make it possible to directly compute locations, sizes, shapes, and pin positions for the leaf cells. >