An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Electrostatic discharge protection in integrated circuits, systems and methods

A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.

Extended drain resurf lateral DMOS devices

Method of forming an electrostatic discharge protection circuit

A semiconductor device (100) which has a resistor (12), a capacitor (13), a Schottky diode (11), and an ESD protection device (101) all formed on a single semiconductor substrate. The resistor (12) and the capacitor (13) are coupled together in series. The Schottky diode and the ESD protection device are coupled in parallel to the series connection of the resistor (12) and capacitor (13).

Semiconductor device with integrated RC network and Schottky diode

A portable semiconductor memory device includes an internal memory for storing data, an address bus, a control bus, and a data bus which are connected to the internal memory, a connector for electrically connecting the address bus, the control bus, and the data bus to terminal equipment, and a contact confirmation/control circuit which is connected to the address bus, the control bus, and the data bus and in which known data is previously stored and which outputs the known data to the data bus when a read control signal is input from the terminal equipment over the control bus and when a given address is specified on the address bus to indicate the proper connection of the memory device to the terminal equipment through the connector.

Portable semiconductor memory device

A single-chip integrated semiconductor device, in which a P-type isolation layer, to which the ground voltage is applied, is grown on a semiconductor substrate and a power voltage is applied to the substrate, in which a vettical MOSFET has a drain region of a first N-type well region formed in the P-type isolation layer so as to reach the semiconductor substrate therethrough, and is used in an output device for a load, in which a P-channel MOSFET is provided in the N-type well region formed in the P-type isolation layer, a constant voltage lower than the power voltage being applied to the N-type well region, and an N-channel MOSFET is formed in the P-type isolation layer, and in which the P-channel and N-channel MOSFETs constitute a CMOS circuit constructing a peripheral circuit for the vertical MOSFET.

Power integrated circuit.

An input protector device for a semiconductor device such as a CMOS device, in which a first resistor is formed on an insulating film of a semiconductor substrate, and a second resistor is formed of an impurity diffusion region in the substrate, the first and second resistors and a capacitor being coupled to one another in series to constitute a filter circuit, and in which first and second diodes each cooperated with at least one of the first and second resistors, by-passing noises having low and high voltages, respectively, and a high frequency noise is cut by the filter circuit, thereby effectively preventing latchup.

Input protector device for semiconductor device

Halbleitervorrichtung mit hoher stromstossfestigkeit

PURPOSE:To make higher a latch-up strength by a method wherein a first n base, a recombined layer having a forbidden band width narrower than that of this first n base and a second n-type base are superposed on a p layer, p base layers and n source layers are provided on the surface, and gate electrodes are each provided on p-type base between both layers through each gate insulating film. CONSTITUTION:A first n Si base layer 3 and an SixGe1-x layer 4 having a forbidden band width smaller than that of the layer 3 are superposed on a p layer 1, and holes which have modulated the conductivity of the layer 3 are recombined and extinguished in the layer 4. Then, a second n-type base layer 5 (substantial drain), a p-type well 6 and an n source 8 are made. A gate electrode 11 is made on a base 7 between the n layer 8 and the n layer 5 through an insulating film 10. The electrode 11 is covered with a PSG film 14, and a source electrode 15 is connected to the p base 7 through the n layer 8 and the p well 6. According to this constitution, holes are sufficiently injected from the layer 1 to drop an ON-state resistance, the holes are extinguished in the recombined layer 4 and do not reach the base 7 and a latch-up strength is increased.

Matsushita Tsutomu

Papers

Power integrated circuit.

Input protector device for semiconductor device

Halbleitervorrichtung mit hoher stromstossfestigkeit

Conductance-modulated mosfet