This paper proposes fast performance reconfigurable pipeline variable points FFT processor design. This design is proposed for variable N points whose values can be 8, 16, 32, 64, 128, 256 and 512 sample points. Hence, the proposed reconfigurable design can be used for different points OFDM applications rather using different designs. The proposed implementation design uses Radix-2 Common Factor Algorithm (CFA) algorithm and SDF architecture. Radix-2 CFA algorithm reduces the number of twiddle factors compared to Radix-4 and Radix-2 and utilizes Radix-2 butterfly structure whose complexity is very low. SDF architecture uses less memory and utilizes multipliers fully compared to others. The frequency of proposed design is varied with the FFT points N. The proposed design is synthesized successfully using XST of Xilinx ISE 14.1 and simulated using ModelSim & MATLAB tool to verify results. Synthesized results of the proposed design for 512 points are 155.9 MHz max frequency, slice used 1795, slices Flip Flops used 1028 and LUTs used 3335 which are approximately 37% higher, 35%, 19%, 27% lesser in ratio than convention FFTs. 

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Fast Performance Pipeline Re-Configurable FFT Processor Based on Radix-22 for Variable Length N

Digital signal Processing (DSP) utilizes The efficient Fast Fourier Transform (FFT) Methodology that is used to alter, filter, and decode digital audio, video, and image data. FFT is used to design Electrical Circuits, to solve differential equations, to analyze signals and to process images. Distributed Arithmetic (DA) is a multiplier-less implementation technique that computes the inner dot product between two signals-fixed and varying by using shifters and adders. It takes the values in a bit-serial fashion which suits for real-time processing. The Computation Logic Blocks (CLBs) of Field Programmable Gate Anays (FPGAs) Utilize Distributed Arithmetic. FFT can be calculated using the DA method. The existing method to calculate FFT is based on complex multiplications and additions which consume time as well as power. Hence DA based FFT has been proposed in which the delay is 29.3% less and the power is 21.8% less than that of the existing method. 

Designing 64-Bit LUT based FFT Structure for High-Speed DSP Applications

Digital signal Processing (DSP) utilizes The efficient Fast Fourier Transform (FFT) Methodology that is used to alter, filter, and decode digital audio, video, and image data. FFT is used to design Electrical Circuits, to solve differential equations, to analyze signals and to process images. Distributed Arithmetic (DA) is a multiplier-less implementation technique that computes the inner dot product between two signals-fixed and varying by using shifters and adders. It takes the values in a bit-serial fashion which suits for real-time processing. The Computation Logic Blocks (CLBs) of Field Programmable Gate Anays (FPGAs) Utilize Distributed Arithmetic. FFT can be calculated using the DA method. The existing method to calculate FFT is based on complex multiplications and additions which consume time as well as power. Hence DA based FFT has been proposed in which the delay is 29.3% less and the power is 21.8% less than that of the existing method.

In Cooley-Tukey algorithm the Radix-2 decimation-in-time Fast Fourier Transform is the easiest form. The Fast Fourier Transform is the mostly used in digital signal processing algorithms. Discrete Fourier Transform (DFT) is computing by the FFT. DFT is used to convert a time domain signal into its frequency spectrum domain. FFT algorithm use many applications for example, OFDM, Noise reduction, Digital audio broadcasting, Digital video broadcasting. It's used to design butterflies for different point FFT. In this paper given to design and power measurement 16 and 32 point FFT by using VHDL. Simulation and synthesis of design is done using Xilinx ISE 14.2.

Mayura Patrikar

Papers

Design and power measurement of different points FFT using Radix-2 algorithm for FPGA implementation