Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead.

https://www.mdpi.com/2072-666X/12/5/560/pdf

High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems.

As technology evolves, embedded systems access more networks and devices, which means more security threats. Existing security-monitoring methods with a single parameter (data or control flow) are not effective in detecting attackers tampering with the data or control flow of an embedded system. However, simply overlaying multiple security methods will result in excessive performance overhead for embedded systems. In this paper, we propose a novel hardware security-monitoring architecture that extracts DI (data integrity) digests and CFI (control flow integrity) tags to generate reference information when the program is offline. To monitor the indirect jumping behavior, this paper maps the legal target addresses into the bitmap, thus saving the search time. When the program is loaded, the reference information and the bitmap are safely loaded into the on-chip memory. The hardware monitoring module designed in this paper will check the DI summary and CFI tags in real time while executing the program. The architecture proposed in this paper has been implemented on the Xilinx Virtex 5 FPGA platform. Experimental results show that, compared with existing protection methods, the proposed approach in this paper can effectively detect multiple tampering-type attacks on the data and control flow of the embedded system, with a performance overhead of about 6%.

https://www.mdpi.com/2076-3417/12/15/7750/pdf?version=1659514181

A Hardware Security-Monitoring Architecture Based on Data Integrity and Control Flow Integrity for Embedded Systems

The hardware security of embedded systems is raising more and more concerns in numerous safety-critical applications, such as in the automotive, aerospace, avionic, and railway systems. Embedded systems are gaining popularity in these safety-sensitive sectors with high performance, low power, and great reliability, which are ideal control platforms for executing instruction operation and data processing. However, modern embedded systems are still exposing many potential hardware vulnerabilities to malicious attacks, including software-level and hardware-level attacks; these can cause program execution failure and confidential data leakage. For this reason, this paper presents a novel embedded system by integrating a hardware-assisted security monitoring unit (SMU), for achieving a reinforced system-on-chip (SoC) on ensuring program execution and data processing security. This architecture design was implemented and evaluated on a Xilinx Virtex-5 FPGA development board. Based on the evaluation of the SMU hardware implementation in terms of performance overhead, security capability, and resource consumption, the experimental results indicate that the SMU does not lead to a significant speed degradation to processor while executing different benchmarks, and its average performance overhead reduces to 2.18% on typical 8-KB I/D-Caches. Security capability evaluation confirms the monitoring effectiveness of SMU against both instruction and data tampering attacks. Meanwhile, the SoC satisfies a good balance between high-security and resource overhead.

Hardware-Assisted Security Monitoring Unit for Real-Time Ensuring Secure Instruction Execution and Data Processing in Embedded Systems

Weighted vertex cover (WVC) is one of the most important combinatorial optimization problems. In this paper, we provide a new game optimization to achieve efficiency and time of solutions for the WVC problem of weighted networks. We first model the WVC problem as a general game on weighted networks. Under the framework of a game, we newly define several cover states to describe the WVC problem. Moreover, we reveal the relationship among these cover states of the weighted network and the strict Nash equilibriums (SNEs) of the game. Then, we propose a game-based asynchronous algorithm (GAA), which can theoretically guarantee that all cover states of vertices converging in an SNE with polynomial time. Subsequently, we improve the GAA by adding 2-hop and 3-hop adjustment mechanisms, termed the improved game-based asynchronous algorithm (IGAA), in which we prove that it can obtain a better solution to the WVC problem than using a the GAA. Finally, numerical simulations demonstrate that the proposed IGAA can obtain a better approximate solution in promising computation time compared with the existing representative algorithms.

Optimizing Polynomial-Time Solutions to a Network Weighted Vertex Cover Game

Embedded applications are commonly used in different fields. Different kinds vulnerabilities can occur in embedded systems because of various reasons such as coding bugs or security attacks. Most of security vulnerabilities can occur during coding phase of an embedded application. During the design phase of a program, different types of coding bugs can be inserted to executable. On the other hand, even if the executable program is very well coded, many different kinds of vulnerabilities can also occur at runtime. In this thesis, we aim to provide a security application which controls integrity of running program in computer. Executable binary of a program consists of data and text sections. CPU fetches and executes instructions in the text section of a program. Each instruction block is firstly placed into instruction cache of CPU. Instruction block hashes are generated after compiler phase of a program. Then, during the runtime phase instruction block hashes are recalculated and compared with compiler phase hash. We aim to prevent running of a corrupted or manipulated program during runtime phase. 

Implementation of Code Integrity Check Module for RISC-V Architecture with AES

Recently, extensive research attention has been drawn to the program executing security of embedded processor since increasing code tamper attacks, as well as transient faults severely affect the safety of embedded systems. The security monitoring and fault recovery technique is one of the effective methods to ensure the security and performance of embedded devices. In this article, an architecture for the security monitoring and fault recovery is proposed for run-time program execution, which builds a Monitoring Cache (M-Cache) and then checks the integrity based on reference data. Especially, the proposed architecture will build the checkpoint once the M-Cache is missed and also take the rollback operation after the unsuccessful of integrity check. In addition, three tampered positions (e.g., instruction register within the pipeline, instruction within the cache, and code within memory) have been elaborately focused on to guarantee the normal running of the embedded system. Eventually, by adopting the open RISC processor for algorithm implementation and verification, the proposal has been proven to be promising for the detection of a fault or tampered program, as well as the fast recovery of running environment and code.

An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor

Nowadays, the secure program execution of embedded processor has attracted considerable research attention, since more and more code tampering attacks and transient faults are seriously affecting the security of embedded processors. The program monitoring and fault recovery strategies are not only closely related to the security of embedded devices, but also directly affect the performance of the processor. This paper presents a security monitoring and fault recovery architecture for run-time program execution, which takes regular backup copies of the two-stage checkpoint. In this framework, the integrity check technology based on the basic block (BB) is utilized to monitor the program execution in real-time, while the rollback operation is taken once the integrity check is failed. In addition, a Monitoring Cache (M-Cache) is built to buffer the reference data for integrity checking. Moreover, a recovery strategy mainly for three tampered positions (registers in processor, instructions in Cache, and codes in memory) is provided to ensure the smooth running of the embedded system. Finally, the open RISC processor is adopted to implement and verify the presented security architecture, which has been proved to be effective for program detection in the execution of tamper attack and quick recovery of the running environment as well as code.

https://www.mdpi.com/2079-9292/9/7/1165/pdf

Mengchen Liu

Papers

An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor

Two-Stage Checkpoint Based Security Monitoring and Fault Recovery Architecture for Embedded Processor