The transfer gate between the master section and the slave section in a flip-flop circuit includes a circuit for reducing the sensitivity to slow clock edges and clock skew. This is accomplished by prolonging the transfer time for data from the master to the salve section of the flip-flop circuit.

Flip-flop circuit having transfer gate delay

A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.

Flip-flops, shift registers, and active-matrix display devices

A CMOS pass gate receiver improves chip-to-chip communication speed for high speed chips. The high speed CMOS pass gate receiver is immune to overshoot or undershoot and can operate in a frequency greater than or equal to 400 Mhz.

High speed off-chip CMOS receiver

A system and method are provided for estimating current. A current source is configured to generate a current and a pulsed sense enable signal is generated. An estimate of the current is generated and the estimate of the current is updated based on a first signal that is configured to couple the current source to an electric power supply and a second signal that is configured to couple the current source to aloud. A system includes the current source and a current prediction unit. The current source is configured to generate a current. The current prediction unit is coupled the current source and is configured to generate the estimate of the current and update the estimate of the current based on the first signal and the second signal.

Predictive current sensing

Disclosed is an analog switch circuit which has: an analog switch which is composed of a P-channel first transistor and a N-channel second transistor whose drains are connected to each other and whose sources are connected to each other; first and second diodes which are in parallel and reversely to each other connected between a back gate of the first transistor and a high-potential power source; and third and fourth diodes which are in parallel and reversely to each other connected between a back gate of the second transistor and a low-potential power source. Further disclosed is an analog switch circuit which has: an analog switch which is composed of a P-channel first transistor and a N-channel second transistor whose drains are connected to each other and whose sources are connected to each other; and a N-channel third transistor whose gate is connected to a high-potential power source and/or a P-channel fourth transistor whose gate is connected to a low-potential power source; wherein the third transistor and/or the fourth transistor are/is in series connected between an input terminal and an input terminal of the analog switch.

Analog switch circuit

A BICMOS passgate circuit (PSGT3) (PSGT3A) for use in latches and flip-flops incorporates a bipolar output circuit (Q1,Q3) comprising a bipolar pullup transistor element (Q1) and a bipolar pulldown transistor element (Q3) coupled to the passgate output (V OUT ) for transient charging and discharging of load capacitance (C L ) at the passgate output (V OUT ) The bipolar output circuit provides increased sinking and sourcing output drive current and s amplification of sinking and sourcing drive current at the passgate output V OUT in response to data signals at the passgate input (V′ IN ) in the transparent operating mode An MOS input logic circuit coupled to the passgate input (V′ IN ) includes clock signal inputs ( CP ¯ , CP ¯ ) for implementing transparent and blocking operating modes The MOS input logic circuit (QP3,QP4,QP5,QP6,NAND1) is coupled to the bipolar output circuit (Q1,Q3) and is constructed to control the conducting states of the bipolar pullup (Q1) and pulldown (Q3) transistor elements for transient turn on of one of the respective bipolar pullup and pulldown transistor elements during respective switching transitions at the passgate output (V OUT ) The MOS input logic circuit is also connstructed for turn off of the bipolar pullup (Q1) and pulldown (Q3) transistor elements follow switching transitions at the output (V OUT ) and during the blocking operating mode A final latchback circuit (LTBK2) (INV3,INV4) is coupled to the passgate output to latch an output data signal and for pulling up the final output (V OUT ) to a high potential level power rail (V CC )

Michael G. Ward

Papers

High speed passgate, latch & flip-flop circuits