I-CYP binding sites) was determinedafter 24 hours of isoproterenol treatment and ex-pressed as the percentage of receptor number as-sessed in nonstimulated cells. Where necessary,MG132 (20 mM) or lactacystin (20 mM) mixed inserum-free media was added to cells 1 hour beforestimulation.16. P. van Kerkhof, R. Govers, C. M. Alves dos Santos, G. J.Strous,

https://cml.harvard.edu/assets/science294_1313.pdf

Logic Gates and Computation from Assembled Nanowire Building Blocks

According to nihseniorhealth.gov (a website for older adults), falling represents a great threat as people get older, and providing mechanisms to detect and prevent falls is critical to improve people's lives. Over 1.6 million U.S. adults are treated for fall-related injuries in emergency rooms every year suffering fractures, loss of independence, and even death. It is clear then, that this problem must be addressed in a prompt manner, and the use of pervasive computing plays a key role to achieve this. Fall detection (FD) and fall prevention (FP) are research areas that have been active for over a decade, and they both strive for improving people's lives through the use of pervasive computing. This paper surveys the state of the art in FD and FP systems, including qualitative comparisons among various studies. It aims to serve as a point of reference for future research on the mentioned systems. A general description of FD and FP systems is provided, including the different types of sensors used in both approaches. Challenges and current solutions are presented and described in great detail. A 3-level taxonomy associated with the risk factors of a fall is proposed. Finally, cutting edge FD and FP systems are thoroughly reviewed and qualitatively compared, in terms of design issues and other parameters.

/pdf/survey-on-fall-detection-and-fall-prevention-using-wearable-4cj6v4b6oy.pdf

Survey on Fall Detection and Fall Prevention Using Wearable and External Sensors

Beyond energy, the growing number of defects in physical substrates is becoming another major constraint that affects the design of computing devices and systems. As the underlying semiconductor technologies are getting less and less reliable, the probability that some components of computing devices fail also increases, preventing designers from realizing the full potential benefits of on-chip exascale integration derived from near atomic scale feature dimensions. As the quest for performance confronts permanent and transient faults, device variation, and thermal issues, major breakthroughs in computing efficiency are expected to benefit from unconventional and new models of computation, such as brain-inspired computing. The challenge is then to find not only high-performance and energy-efficient, but also fault-tolerant computing solutions. Neural computing principles remain elusive, yet as source of a promising fault-tolerant computing paradigm. In the quest to fault tolerance can be translated into scalable and reliable computing systems, hardware design itself and/or to use circuits even with faults has further motivated research on neural networks, which are potentially capable of absorbing some degrees of vulnerability based on their natural properties. This paper presents a survey on fault tolerance in neural networks manly focusing on well-established passive techniques to exploit and improve, by design, such potential but limited intrinsic property in neural models, particularly for feedforward neural networks. First, fundamental concepts and background on fault tolerance are introduced. Then, we review fault types, models, and measures used to evaluate performance and provide a taxonomy of the main techniques to enhance the intrinsic properties of some neural models, based on the principles and mechanisms that they exploit to achieve fault tolerance passively. For completeness, we briefly review some representative works on active fault tolerance in neural networks. We present some key challenges that remain to be overcome and conclude with an outlook for this field.

Fault and Error Tolerance in Neural Networks: A Review

Натрийуретические пептиды (НУП) являются важными биомаркерами в диагностике и определении прогноза у пациентов с сердечной недостаточностью (СН). Оценка динамики концентрации НУП (BNP, Nt -proBNP) может быть использована в качестве критерия успешности проводимой терапии. так, при достижении целевых уровней НУП можно прогнозировать благоприятный исход заболевания. В настоящее время лечение СН с учетом уровней НУП является частью рекомендаций по лечению СН (класс IIа) и улучшению ее исхода (класс IIб) в США, однако такой подход не используется в российских клиниках. Цель. Представить современный взгляд на возможность использования НУП для оценки эффективности проводимой терапии пациентов с СН. Ключевые слова: натрийуретические пептиды, сердечная недостаточность, оценка эффективности терапии.

Федеральное государственное бюджетное учреждение «Научно-исследовательский институт комплексных проблем сердечно-сосудистых заболеваний» Сибирского отделения Российской академии медицинских наук, Кемерово, Россия

In this survey paper, we compare native double precision solvers with emulated-and mixed-precision solvers of linear systems of equations as they typically arise in finite element discretisations. The emulation utilises two single float numbers to achieve higher precision, while the mixed precision iterative refinement computes residuals and updates the solution vector in double precision but solves the residual systems in single precision. Both techniques have been known since the 1960s, but little attention has been devoted to their performance aspects. Motivated by changing paradigms in processor technology and the emergence of highly-parallel devices with outstanding single float performance, we adapt the emulation and mixed precision techniques to coupled hardware configurations, where the parallel devices serve as scientific co-processors. The performance advantages are examined with respect to speedups over a native double precision implementation (time aspect) and reduced area requirements for a chip (space aspect). The paper begins with an overview of the theoretical background, algorithmic approaches and suitable hardware architectures. We then employ several conjugate gradient (CG) and multigrid solvers and study their behaviour for different parameter settings of the iterative refinement technique. Concrete speedup factors are evaluated on the coupled hardware configuration of a general-purpose CPU and a graphics processor. The dual performance aspect of potential area savings is assessed on a field programmable gate array (FPGA). In the last part, we test the applicability of the proposed mixed precision schemes with ill-conditioned matrices. We conclude that the mixed precision approach works very well with the parallel co-processors gaining speedup factors of four to five, and area savings of three to four, while maintaining the same accuracy as a reference solver executing everything in double precision.

/pdf/performance-and-accuracy-of-hardware-oriented-native-tfk7suy752.pdf

Performance and accuracy of hardware-oriented native-, emulated-and mixed-precision solvers in FEM simulations

While most of the electronics industry is dependent on the ever-decreasing size of lithographic tran- sistors, this scaling cannot continue indefinitely. Nanoelectro- nics (circuits built with components on the scale of 10 nm) seem to be the most promising successor to lithographic based ICs. Molecular-scale devices including diodes, bistable switches, carbon nanotubes, and nanowires have been fab- ricated and characterized in chemistry labs. Techniques for self-assembling these devices into different architectures have also been demonstrated and used to build small-scale proto- types. While these devices and assembly techniques will lead to nanoscale electronics, they also have the drawback of being prone to defects and transient faults. Fault-tolerance techni- ques will be crucial to the use of nanoelectronics. Lastly, changes to the software tools that support the fabrication and use of ICs will be needed to extend them to support nano- electronics. This paper introduces nanoelectronics and reviews the current progress made in research in the areas of tech- nologies, architectures, fault tolerance, and software tools.

The Future of Integrated Circuits: A Survey of Nanoelectronics Nano-devices, such as molecules that function as computer switches as well as silicon wires and carbon tube interconnections, have been fabricated and demonstrated, and further research is underway.

There have been many papers proposing the use of logarithmic numbers (LNS) as an alternative to floating point because of simpler multiplication, division and exponentiation computations. However, this advantage comes at the cost of complicated, inexact addition and subtraction, as well as the need to convert between the formats. In this work, we created a parameterized LNS library of computational units and compared them to an existing floating point library. Specifically, we considered multiplication, division, addition, subtraction, and format conversion to determine when one format should be used over the other and when it is advantageous to change formats during a calculation.

/pdf/a-comparison-of-floating-point-and-logarithmic-number-42zezg9nxn.pdf

A comparison of floating point and logarithmic number systems for FPGAs

Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanner. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper two such processes, sub-clock rate pulse timing and event localization, will be discussed in detail. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC. We will also show that the position of events in the scanner can be determined in real time using a statistical positioning based algorithm.

/pdf/fpga-based-front-end-electronics-for-positron-emission-3b7g8acbbr.pdf

FPGA-based front-end electronics for positron emission tomography

Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates well above 100 MHz This, combined with FPGA's low expense and ease of use, make them an ideal technology for pulse timing and are a central part of our next generation of electronics for our pre-clinical PET scanner systems To that end, our laboratory has been developing a pulse timing technique that uses pulse fitting to achieve timing resolution well below the sampling period of the analog to digital converter (ADC) While ADCs with sampling rates in excess of 400 MS/s exist, we feel that using ADCs with lowing sampling rates has many advantages for positron emission tomography (PET) scanners It is with this premise that we have started simulating timing algorithms using MATLAB in order to optimize the parameters before implementing the algorithm in Verilog MATLAB simulations allow us to quickly investigate filter designs, ADC sampling rates and algorithms with real data before implementation in hardware We report our results for a least squares fitting algorithm and a new version of a leading edge detector of PMT pulses

/pdf/simulation-of-algorithms-for-pulse-timing-in-fpgas-4on865eg0g.pdf

Simulation of algorithms for pulse timing in FPGAs

Developing new detector designs for PET and SPECT imaging systems often leads to problems in adapting existing data acquisition electronics to the requirements for the new devices. As we developed depth-of-interaction detector designs based on both discrete crystal arrays (dMiCE) and monolithic crystals (cMiCE) concepts, we found that our previous electronics design was inadequate to the task and launched a design effort we have termed our Phase II electronics. The system is based on a basic card design (the Phase II board) that has a large field programmable gate array (FPGA) with sufficient static RAM to support a variety of pulse processing algorithms our group has developed - including timing estimation, pulse integration with pileup correction, and statistical estimation of the event location in the detector. The Phase II board can be configured to take on several roles, including a master/coincidence controller, an acquisition node handling up to 64 channels of analog data digitized at 65 MHz and one channel digitized at >300 MHz, an acquisition node supporting up to 64 serial data inputs (e.g., from devices like digital silicon photomultipliers), or as an acquisition node that takes in data from other Phase II boards in a star configuration to expand the number of detector modules the system can support. The current implementation is based on FireWire (limiting the total number of acquisition nodes directly connect to the bus to 62), but future versions are planned to support USB and PCIexpress. Here we report on the testing of the first prototype Phase II main board supporting a 64 channel cMiCE detector and describe the current development plans for the system.

/pdf/evolution-of-the-design-of-a-second-generation-firewire-1advb8ksz2.pdf

Michael Haselman

Papers

The Future of Integrated Circuits: A Survey of Nanoelectronics Nano-devices, such as molecules that function as computer switches as well as silicon wires and carbon tube interconnections, have been fabricated and demonstrated, and further research is underway.

A comparison of floating point and logarithmic number systems for FPGAs

FPGA-based front-end electronics for positron emission tomography

Simulation of algorithms for pulse timing in FPGAs

Evolution of the design of a second generation FireWire based data acquisition system