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Michael John Sebastian Smith

Researcher at Google

Publications -  71
Citations -  4430

Michael John Sebastian Smith is an academic researcher from Google. The author has contributed to research in topics: Memory refresh & Registered memory. The author has an hindex of 40, co-authored 71 publications receiving 4428 citations. Previous affiliations of Michael John Sebastian Smith include Marathon Oil.

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Patent

Automatically providing content associated with captured information, such as information captured in real-time

TL;DR: In this paper, a system and method for automatically providing content associated with captured information is described, in which the system receives input by a user, and automatically provides content or links to the information associated with the input.
Patent

Methods and apparatus of stacking DRAMs

TL;DR: In this paper, large capacity memory systems are constructed using stacked memory integrated circuits or chips, which are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
Patent

Automatically capturing information such as capturing information using a document-aware device

TL;DR: A system and method for automatically changing the operation of a mobile device in response to a presence of information is described in this article, where the system determines an information capture device is proximate to text, automatically changes operation of the capture device to a certain mode, captures the text, and performs an action associated with the captured text.
Patent

Associating rendered advertisements with digital content

TL;DR: In this paper, a system and method for associating rendered advertisements with digital content is described, where the system receives an image of a rendered advertisement, information associated with digital contents, and information associating the rendered advertisement with the digital content via a web portal.
Patent

Memory circuit system and method

TL;DR: In this paper, a memory circuit system and method for communication with a plurality of DRAM integrated circuits and a system is presented, where the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.