A method of fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12), forming on the surface (12) of the silicon substrate (10), by atomic layer deposition (ALD), a seed layer (20;20') characterised by a silicate material and forming, by atomic layer deposition (ALD) one or more layers of a high dielectric constant oxide (40) on the seed layer (20;20').

Method for fabricating a semiconductor structure including a metal oxide interface with silicon

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same

An integrated circuit is presented in which optical signal propagation replaces or supplements conventional electrical signal propagation. Optical lasers, waveguides, beam splitters, and photodetectors are fabricated on top of or below conventional electrical semiconductor circuits to propagate data, clock, and control signals. Such optical signal propagation is generally more rapid than electrical signal propagation, and can free conventional electrical semiconductor circuit area by eliminating at least some conventional data busses and global clock and control wiring. Furthermore, optical clock signal propagation substantially eliminates clock skewing problems and reduces power consumption by significantly eliminating clock signal re-buffering.

Integrated circuits with optical signal propagation

Structure and method for fabricating semiconductor structures and devices for detecting an object

A hybrid integrated circuit is provided that has a monocrystalline substrate such as silicon and a compound semiconductor layer such as gallium arsenide or indium phosphide An optical communications port may be formed on the hybrid integrated circuit Electrical equipment may be provided that includes electrical components At least a given one of the components may be a hybrid integrated circuit Data used for the operation of one of the given integrated circuit may be provided to the given integrated circuit through the optical communications port on that integrated circuit The data may be loaded rapidly in real time due to the wide bandwidth of the optical communications port

Reconfigurable systems using hybrid integrated circuits with optical ports

A method of fabricating submicron HFETs includes forming a buffered substrate structure with a supporting substrate of GaAs, a portion of low temperature AlGaAs grown on the supporting substrate at a temperature of approximately 300° C., a layer of low temperature GaAs grown on the portion AlGaAs layer at a temperature of 200° C., a layer of low temperature AlGaAs grown on the GaAs layer at a temperature of 400° C., and a buffer layer of undoped GaAs grown on the second AlGaAs layer. Complementary pairs of HFETs can be formed on the buffered substrate structure, since the structure supports the operation of p and n type transistors equally well.

Method of fabricating submicron FETs with low temperature group III-V material

A digital clock generator circuit which accepts a rate signal and a master clock signal and generates an output clock signal exhibiting a frequency which is programmed by the rate signal is disclosed. A constant duty cycle characteristic of the output clock signal is obtained regardless of the output clock signal's frequency. A memory element which generates the output signal is placed in one logical state when a counter portion of the present invention reaches a terminal count. The memory element is placed in an opposing logical state whenever the counter achieves 1/2 of its programmed value. A duty cycle compensator makes small timing adjustments to compensate for any truncation error which occurs in dividing the rate signal by two.

Constant duty cycle, frequency programmable clock generator

A method of evaluating a cryptosystem to determine whether the cryptosystem can withstand a fault analysis attack, the method includes the steps of providing a cryptosystem having an encrypting process to encrypt a plaintext into a ciphertext, introducing a fault into the encrypting process to generate a ciphertext with faults, and comparing the ciphertext with the ciphertext with faults in an attempt to recover a key of the cryptosystem.

Differential fault analysis hardening apparatus and evaluation method

A method and apparatus for hardening current steering logic (CSL) to soft errors (charged particles passing through and upsetting the logic state of an integrated circuit) includes a hardened CSL circuit or cell (20), including three or more circuit cell elements (21) in parallel. The circuit cell elements (21) redundantly perform a single cell function. Each of the circuit cell elements (21) is coupled to soft error immune resistive elements (24 and 25) within a summing element (22). Current (23) is steered through the resistive elements (24 and 25) depending upon input signals (26) to each of the circuit cell elements (21). The logical output signal (27) is unaffected by a single soft error event since the majority of the total current (23) remains steered through the correct resistive element (24 or 25).

Method and apparatus for hardening current steering logic to soft errors

A single event upset (SEU) sensitivity control system (42) dynamically hardens a digital circuit (48) to single event upsets. The sensitivity control system (42) includes an upset rate sensor (66) for detecting a quantity of particles (38) that cause single event upsets. A noise margin control circuit (70) is configured to adjust a noise margin (46) of the digital circuit (48) in response to the quantity of particles (38). Noise margin (46) is increased when a particle density (34) is high to decrease the sensitivity of the digital circuit (48) to single event upsets. Additionally, noise margin (46) is decreased when a particle density (36) is low to decrease the power consumption level of digital circuit (48).

Michael P. LaMacchia

Papers

Method of fabricating submicron FETs with low temperature group III-V material

Constant duty cycle, frequency programmable clock generator

Differential fault analysis hardening apparatus and evaluation method

Method and apparatus for hardening current steering logic to soft errors

Apparatus and method for dynamic hardening of a digital circuit