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Michael P. Nova

Publications -  5
Citations -  362

Michael P. Nova is an academic researcher. The author has contributed to research in topics: Wireless network & Network architecture. The author has an hindex of 5, co-authored 5 publications receiving 362 citations.

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Patent

System and method for identifying nodes in a wireless network

TL;DR: In this paper, a boundary scan test of a wired or wireless network having a plurality of network nodes is presented, which includes a test station communicatively coupled with the network and a test agent that is configured to traverse each link in the scan test route sequence.
Patent

System and method for routing packets in a wired or wireless network

TL;DR: In this article, the authors present an attribute routing scheme that routes communication packets that include objects containing network optimization parameters that are used to control the physical links in the network, which allows objects having new optimization parameters beyond the conventional network topology parameters or network link parameters to be defined and propagated throughout the network.
Patent

Systems and methods for network based sensing and distributed sensor, data and memory management

TL;DR: In this article, the authors present a system, architectures and methods of operation and use of remotely spaced sensors (50) and component arrangements of sensors, actuators, and networks, which provide the collection, analysis and action upon sensed information at multiple remote locations.
Patent

System and method for boundary scan test of a wired or wireless network

TL;DR: In this article, a boundary scan test of a wired or wireless network having a plurality of network nodes is presented, which includes a test station communicatively coupled with the network and a test agent that is configured to traverse each link in the scan test route sequence.
Patent

System and method for machine to machine communication

TL;DR: In this article, a machine to machine (M2M) communication over a communication network is presented, which can be implemented as an ASIC, sea of gates, or mask programmed CPU.