A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.

256 Meg dynamic random access memory

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A circuit including an oscillator circuit, a current generator circuit and a voltage generator circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The current generator may be configured to generate said first control signal in response to a first adjustment signal. The voltage generator circuit may be configured to generate the second control signal in response to a second adjustment signal.

Programmable oscillator scheme

A charge pump power converter efficiently provides electrical power by dynamically controlling a switch matrix of the charge pump. Instead of open-loop oscillator-based control, a dynamic controller provides power upon demand by sensing the output voltage and changing the operating frequency of the charge pump in response. Moreover, this closed-loop dynamic control intrinsically voltage regulates the output voltage of the charge pump power converter without the inefficient addition of a step-down voltage regulator, downstream of the power converter. Additional efficiencies are achieved through maintaining the voltage ripple across the fly capacitor and/or the load capacitor. Also, a three-state control scheme is used to charge the fly capacitor, wait for the output voltage to drop to a predetermined level, and discharge the fly capacitor. Furthermore, a multiple-output charge pump power converter provides multiple voltage levels for devices such as portable communication electronic devices.

Multiple output dynamically regulated charge pump power converter

A memory cell array (12, 22) or selected blocks (32-36) thereof may be made inactive to reduce leakage current and power consumption. A switch (14, 26, 40-44, 116, 134, 139) is coupled between the memory cell array (12, 22, 96-100, 112, 132) or segmented memory blocks (32-36) and the power supply. The switch (14, 16, 40-44) are controlled to selectively connect the memory cell array (12, 22, 96-100, 112, 132) or blocks thereof (32-36) to the power supply according to the active, standby, or disabled operation states of the memory. The periphery circuitry (114) may also be powered separately from the memory cell array (112) to further reduce leakage currents and power consumption.

Selective power to memory

A voltage generator for low power applications includes a circuit for generating, controlling and maintaining a high voltage for low power applications in an integrated circuit. The circuit includes separate standby and active circuits for pumping VCCP of a DRAM under different circumstances. The standby and active circuits operate independently of one another, but may operate simultaneously, to pump charge to VCCP. The standby circuit is generally a low power circuit activated in response to power up and leakage current conditions to maintain VCCP. The active circuit is generally a larger circuit and can pump more current. The active circuit is generally responsive to the word lines being driven. Accordingly, the voltage generator can maintain VCCP while minimizing power consumption in DRAM.

High voltage generator having a self-timed clock circuit and charge pump, and a method therefor

57 A constant current source (100) is used to provide a constant current (1 2 ) to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor (200) with the constant current (1 2 ). Because the current (1 2 ) is independent of variations in the power supply voltage (V cc ) and temperature, the capacitor (200) will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in the power supply voltage (V cc ) or temperature. A current limiting circuit (300) and latch (400) are provided to generate an output (PULSE A) which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier (600) is provided between the delay circuit (200) and the current limiting circuit (300). This differential amplifier (600) is typically needed in a case where the power supply voltage (V cc ) is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output (PULSE A) for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.

Low power VCC and temperature independent oscillator

A wide range power supply for integrated circuits includes a voltage-down converter to receive the input supply voltage and generate a controlled low voltage signal. The circuit also includes a voltage-up converter which receives the controlled low voltage signal to generate a high voltage signal for high power circuits. Finally, a substrate bias generator is employed in the circuit to generate a substrate bias signal. Because the low power voltage is controlled, the high power voltage and the substrate bias signal are independent of any variations in input supply voltage. In alternate embodiments, the voltage-up converter or voltage-down converter can be disabled if the external supply voltage is controlled and maintained in at high or low voltage respectfully.

Wide range power supply for integrated circuits

A reference voltage generator which compensates for temperature and V CC variations includes a constant current source and a MOS P-channel transistor. The constant current source provides a constant current over a wide range of V CC that corresponds to biasing a p-channel transistor in a region where its resistance is constant. The output of the current source is supplied to the P-channel transistor, which is in saturation. The constant current provides a constant voltage drop across the P-channel transistor. Hence, a stable reference voltage is generated. Temperature compensation is provided by biasing the P-channel transistor to saturation and supplying a constant current that the corresponds to biasing a p-channel transistor where the resistance is substantially constant over a temperature range. The current causes a voltage drop across the P-channel transistor to maintain a stable reference voltage. Also, temperature compensation is further provided by utilizing the negative temperature coefficients of the resistors included in the constant current source.

Temperature compensated voltage reference for low and wide voltage ranges

A negative charge pump circuit for low voltage and wide voltage range applications. The charge pump includes two single-stage p-type pumps. One of the pumps (11) is used to charge a circuit node (32) down to a threshold voltage |Vt p | less than a desired voltage. When used in such a way, the other pump will charge a substrate to a full -VCC.

Michael V Cordoba

Papers

High voltage generator having a self-timed clock circuit and charge pump, and a method therefor

Low power VCC and temperature independent oscillator

Wide range power supply for integrated circuits

Temperature compensated voltage reference for low and wide voltage ranges

Efficient negative charge pump