A computer system in a fault-tolerant configuration employees multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown.

Fault-tolerant computer system with online recovery and reintegration of redundant components

A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas. The transfer of the supervisor function from processor to processor is performed by registering the supervisor's identity in a common area in one of the dedicated interface units which area is accessable to all processors in the associated group and using program interrupts generated in the common interface unit to communicate between group processors. Access to the common system bus by the processing elements is controlled by the associated interface units by means of a combination serial/parallel arbitration scheme which increases arbitration speed without requiring a full complement of request/grant leads.

Modular computer system

A method and apparatus for synchronizing a plurality of processors. Each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit associated with the processor, the sync logic circuit generates the wait signal after the next processor event. A compare circuit associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor. At that time, all processors are synchronized and may be restarted for servicing the event. If no synchronizing event occurs before an event counter reaches its maximum value, and overflow of the event counter forces resynchronization. A cycle counter is provided for counting the number of clock cycles since the last processor event. The cycle counter is set to overflow and force resynchronization at a point before maximum interrupt latency time is exceeded.

Method and apparatus for synchronizing a plurality of processors

A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs are loosely synchronized, as by counting events such as operating cycles and stalling any CPU ahead of others. Data output references via separate busses are voted at separate ports of each of the CPUs by voting circuits which detect when all CPUs have made the same reference, and only then pass on identical references to external I/O busses. The ports may include FIFO buffers to allow output references from the asynchronous CPUs to be handled as the CPUs load the FIFOs at different times. Input data to the CPUs from the I/O busses is not voted, but is buffered to allow the CPUs to accept it at their own clock rate.

Multiple-processor computer system with asynchronous execution of identical code streams

A cache memory capable of concurrently accepting and working on completion of more than one cache access from a plurality of processors connected in parallel. Current accesses to the cache are handled by current-access-completion circuitry which determines whether the current access is capable of immediate completion and either completes the access immediately if so capable or transfers the access to pending-access-completion circuitry if not so capable. The latter circuitry works on completion of pending accesses; it determines and stores for each pending access status information prescribing the steps required to complete the access and redetermines that status information as conditions change. In working on completion of current and pending accesses, the addresses of the accesses are compared to those of memory accesses in progress on the system.

Digital computer with cache capable of concurrently handling multiple accesses from parallel processors

A data processing system includes at least two processors, each having a cache memory containing an index section and a memory section. A first processor performs a task by deriving internal requests for its cache memory which also may respond to an external request derived from the other processor which is simultaneously processing a task. To avoid a conflict between the simultaneous processing of an internal request and of an external request by the same cache memory, one request may act on the other by delaying its enabling or by suspending its processing from the instant at which these requests are required to operate simultaneously on the index section or the memory section of the cache memory of the processor affected by these requests. Thereby, the tasks are performed by the system at an increased speed.

Process and device for managing the conflicts raised by multiple access to same cache memory of a digital data processing system having plural processors, each having a cache memory

L'invention a pour objet un procede et un dispositif pour augmenter la rapidite des tâches executees par un systeme da traitement numerique de l'information. The invention has for object a process and a device for increasing the speed of the tasks performed by a da digital information processing system. Soit un systeme possedant au moins deux processeurs (CPU1, CPU2) possedant chacun un cache (C1, C2) ayant une partie repertoire (DY1, DY2) et une partie memoire M1, M2). Or a system having at least two processors (CPU 1, CPU 2) each having a cache (C1, C2) having a directory section (DY1, DY2) and a memory portion M1, M2). Un processeur (CPU1) execute une tâche en emettant des requetes internes pour son cache qui peut recevoir une requete denommee externe venant de l'autre processeur (CPU2) qui traite lui-meme une tâche. A processor (CPU 1) performs a task by issuing internal requests for its cache that can receive an external application called from the other processor (CPU 2) which deals itself a task. Pour eviter un conflit entre le traitement simultane d'une requete interne et d'une requete externe par un meme cache (C1), une requete peut agir sur l'autre en retardant sa validation ou en suspendant son traitement, des l'instant ou ces requetes desirent travailler simultanement sur la partie repertoire (DY1) ou la partie memoire (M1) du cache (C1) du processeur (CPU1) concerne par ces requetes. To avoid a conflict between simultaneous processing of an internal request and an external request by a same cache (C1), a query can influence the other by delaying its validation or suspending treatment, from the moment these queries want to work simultaneously on the directory section (DY1) or memory section (M1) cache (C1) of the processor (CPU 1) concerned by these requests. L'invention s'applique notamment a des systemes multiprocesseurs. The invention is particularly applicable to multiprocessor systems.

Method and device to control the conflicts posed by multiple accesses to a same cache-memory of a digital data processing system comprising at least two processors each possessing a cache

L'invention a pour objet un procede et un dispositif pour augmenter la rapidite des tâches executees par un systeme da traitement numerique de l'information Soit un systeme possedant au moins deux processeurs (CPU1, CPU2) possedant chacun un cache (C1, C2) ayant une partie repertoire (DY1, DY2) et une partie memoire M1, M2) Un processeur (CPU1) execute une tâche en emettant des requetes internes pour son cache qui peut recevoir une requete denommee externe venant de l'autre processeur (CPU2) qui traite lui-meme une tâche Pour eviter un conflit entre le traitement simultane d'une requete interne et d'une requete externe par un meme cache (C1), une requete peut agir sur l'autre en retardant sa validation ou en suspendant son traitement, des l'instant ou ces requetes desirent travailler simultanement sur la partie repertoire (DY1) ou la partie memoire (M1) du cache (C1) du processeur (CPU1) concerne par ces requetes L'invention s'applique notamment a des systemes multiprocesseurs

Procédé et dispositif pour gérer les conflits posés par des accès multiples à un même cache d'un système de traitement numérique de l'information comprenant au moins deux processeurs possédant chacun un cache

Michel Isert

Papers

Process and device for managing the conflicts raised by multiple access to same cache memory of a digital data processing system having plural processors, each having a cache memory

Method and device to control the conflicts posed by multiple accesses to a same cache-memory of a digital data processing system comprising at least two processors each possessing a cache

Procédé et dispositif pour gérer les conflits posés par des accès multiples à un même cache d'un système de traitement numérique de l'information comprenant au moins deux processeurs possédant chacun un cache