A digital data separator operates to separate data pulses from clock pulses in MFM encoded signals read from a magnetic disk system. The data separator includes a digital phase-locked loop system incorporating a variable length shift register which functions as a variable oscillator and programmed state machines which control the operation of the shift register and provides filtering functions. The state machines filter high frequency noise components from the incoming data signals and enables the system to accurately track frequency variations in the data stream while providing high tolerance to high frequency noise.

High order digital phase-locked loop system

A unique bit data operated squelch for use with a demodulator detector for phase shift keyed digital signals. The squelch detects transitions by testing a register of baseband demodulated sample synchronized to the data bit edges. The inventive data operated squelch provides bit detection with programmable parameters and is particularly suitable for implementation utilizing a microprocessor.

Bit data operated squelch

An electronic system for providing a stable, isochronous clock signal with very low jitter and slew rate to thereby permit multiplexing of data from an external source which is not synchronous with the multiplexer frame rate.

Isochronous clock reconstruction

A digital phase acquisition circuit includes logic for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for a clock for recovering information representative of the data. The circuit allows clock to be recovered within 1 bit time of a predetermined data transition occurring, thus allowing preambles of 1 bit to be utilized in data packets.

Clock recovery apparatus

In a method of embedding a hidden message in digital data, employing plurality of orthogonal random arrays of numbers as carriers for the bits of the hidden message, the random arrays are generated by applying a plurality of unique cyclical shifts to a single random array. In a preferred embodiment, the method is applied to digital image data and the cyclical shifts are defined as locations in a shift template, wherein the shift template has a highly peaked autocorrelation. The shift template is employed to recover the hidden message from the image without the need for calibration signals to indicate the boundaries of the hidden message.

Linear projective data embedding

Demodulator for phase modulated carrier pulse signals or phase codes in which the pulses are coded according to a plurality of N phases of the carrier. It comprises a digital phase lock loop system for locking to a frequency equal to N times the carrier frequency which includes at least a two input phase detector, a loop integrator and a voltage controlled oscillator having an output connected to the first input of the phase detector, means for dividing by N the frequency of this oscillator and for generating a reference carrier signal. The phase codes are decoded by comparing the phases of the carrier of the phase codes to the phase of the reference signal. In order to derive from all the phase codes a train of synchronous pulses a multiphase shifter receives the carrier of the phase codes and locally generates a plurality of carriers having phase shifts equal to 0, 2π/N, 2×2π/N, . . . ([N/2]- 1) ×2π/N with respect to the carrier of the received phase code and means are provided for generating passing through zero pulses coinciding with the passage through zero of said received and locally generated carriers. Those of said passing through zero pulses which occur during the central part of each phase modulated carrier pulse are gated through gating means. These gated passing through zero pulses are applied to the second input of the phase detector.

Michel J. Maitre

Papers

Phase lock loop carrier generator for receiver of phase modulated carrier pulse signals