This paper presents a fully integrated galvanically isolated dc–dc converter with data communication. The converter, which is fabricated in a 0.35- $\mu \text{m}$ BCD technology, is made up of only two silicon dice and adopts two 6-kV on-chip transformers. It takes advantage of a customized architecture, which uses the isolated power control link to transfer bidirectional half-duplex data, thus reducing the overall silicon area and package size. The proposed dc–dc converter delivers up to 93-mW output power with 19% maximum power efficiency and an output voltage ranging from 2.4 V to 3.3 V, while achieving a data rate up to 50 Mb/s.

A Fully Integrated Galvanically Isolated DC-DC Converter With Data Communication

An oscillator for a signal isolator system includes a capacitor and an inductor connected in parallel, two pairs of cross-coupled switches and a control switch. The capacitor, the inductor and the cross-coupled switches form an oscillator. The control switch controls operation of the oscillator between an ON state and an OFF state in response to a data signal to be communicated across an isolation barrier. The inductor may be formed from a winding of an isolation transformer, which reduces component count as compared to a system that provides a separate inductor. Other embodiments may include a current-supplying kickstart circuit and a shorting transistor that can speed transition between the ON and OFF states.

Methods and structures to generate on/off keyed carrier signals for signal isolators

A receiver system for an on-off key ("OOK") isolator system may include a receiver that generates an intermediate current signal based on an OOK input signal. The intermediate current may be provided at a first current level when the input signal has a first OOK state and a second current level when the input signal has a second OOK state. The system also may include an output driver to generate a voltage representation of the intermediate current signal. Performing signal processing in a current domain permits fast transitions between OOK states.

Demodulation of on-off-key modulated signals in signal isolator systems

A method for controlling an antenna network quality factor of an NFC device includes: determining whether a first data rate or a second data rate should be used for data communication during different time intervals, respectively; and when it is determined that the first data rate should be used during a first time interval of the time intervals, controlling a set of internal resistors positioned within a chip of the NFC device to have a first configuration during the first time interval, in order to adjust the antenna network quality factor. More particularly, the method further includes: when it is determined that the second data rate should be used during a second time interval of the time intervals, controlling the set of internal resistors to have a second configuration during the second time interval, in order to adjust the antenna network quality factor. An associated apparatus is also provided.

Method for controlling an antenna network quality factor of a near field communication device without changing matching network, and associated apparatus

An isolator system has an isolator that generates differential isolator signals and a receiver that generates digital data representative of signals received from the isolator. The system also may include an RC filter coupled between the isolator and the receiver. During operation, the filter may distribute transient signals across various circuit paths in the isolator, only some of which are coupled to the receiver inputs. Over time, the filter may attenuate transient contributions at the receiver inputs. In this manner, the filter may limit effects of these common mode transients.

Signal isolator system with protection for common mode transients

A receiver of a signal communication apparatus; the apparatus having a transmitter for transmitting the signals, the receiver for receiving the signals and a galvanically isolated wireless interface interposed between the transmitter and the receiver and having a transmitting antenna and a receiving antenna. The receiver including a disturbance rejection circuit coupled to the receiving antenna and capable of compensating for the parasite currents flowing between the transmitting antenna and the receiving antenna at the potential variations between the input and output of the galvanic isolation interface.

Receiver for signal communication system with disturbance rejection circuit

A receiver of a signal communication apparatus; the apparatus including a transmitter adapted to transmit coded signals, the receiver for receiving the signal and a wireless interface interposed between the transmitter and the receiver and having a transmitting antenna and a receiving antenna. The receiver includes a decoder configured to decode the received signal and circuitry coupled to the receiving antenna and capable of triggering the decoder if the value of the received signal is outside a logical hysteresis having a first logic threshold having a value smaller than the value of the direct current component of the received signal and a second logic threshold having a value greater than the value of the direct current component of the received signal.

Receiver for signal communication apparatus and related signal communication apparatus

There is described a receiver (4) of a signal communication apparatus; the apparatus comprises a transmitter (1) adapted to transmit coded signals, the receiver (4) for receiving the signal and a wireless interface (3) interposed between the transmitter and the receiver and comprising a transmitting antenna (L1) and a receiving antenna (L2). The receiver comprises decoding means (12) of the received signal and first means (9, 10) coupled to the receiving antenna (L2) and capable of triggering said decoding means of the received signal if the value of the received signal is outside a logical hysteresis consisting of a first logic threshold (TH_LO) having a value smaller than the value of the direct current component of the received signal and a second logic threshold (TH_HI) having a value greater than the value of the direct current component (Irde) of the received signal.

Signal communication apparatus and related receiver

There is described a receiver (4) of a signal communication apparatus; the apparatus comprising a transmitter (1) for transmitting the signals, the receiver (4) for receiving the signals and a galvanically isolated wireless interface (3) interposed between the transmitter and the receiver and comprising a transmitting antenna (L1) and a receiving antenna (L2). The receiver comprises a disturbance rejection circuit (6, 52) coupled to the receiving antenna (L2) and capable of compensating for the parasite currents flowing between the transmitting antenna and the receiving antenna at the potential variations between the input and output of the galvanic isolation interface.

Michele Grande

Papers

Receiver for signal communication system with disturbance rejection circuit

Receiver for signal communication apparatus and related signal communication apparatus

Signal communication apparatus and related receiver

Receiver for signal communications with disturbances rejection