Return path clocking mechanism for a system including a master device connected to a plurality of slave devices via a bus. The master device may first generate a global clock. The master device may transmit data to one or more of the slave devices at a rate of one bit per clock cycle. One or more of the slave devices may transmit data to the master device at a rate of one bit per two consecutive clock cycles. The master device may sample the transmitted data on the second cycle of each two consecutive clock cycle period. Alternatively, the slave devices may transmit data to the master device at a rate of one bit per N consecutive clock cycles, where N≧2, and the master device may sample the transmitted data on the N th cycle of each N consecutive clock cycle period.

Two-cycle return path clocking

PURPOSE: To cause a transfer clock frequency to be close to an operating clock frequency by successively instructing the operation of plural synchronous circuits for reception synchronously to the effective change of a transfer clock and operating the plural synchronous circuits for reception in parallel. CONSTITUTION: An allotment circuit 40 generates and allots allotting signals RXCa and RXCb, whose high levels are not overlapped, synchronously to the effective edge change of a transfer clock RXC with being alternatively changed at every cycle of a transfer clock TXC. One allotting signal RXCa to be generated in this circuit 40 is supplied to a clock input terminal CK of FFs 23 and 27 and the other allotting signal RXCb is supplied to the clock input terminal of FFs 30 and 34. The allotting signals RXCa and RXCb are alternatively controlled to the high level synchronously to the cycle of the transfer clock RXC. Accordingly, the instruction of synchronizing operation to synchronous circuits 21 and 22 is alternatively given at every cycle of the transfer clock RXC. Thus, the respective synchronizing circuits 21 and 22 can define the almost two cycles of the transfer clock RXC as a maximum synchronization operatable period to 1 bit data. COPYRIGHT: (C)1990,JPO&Japio

Michio Asano

Papers

Parallel synchronizing circuit