A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Nonplanar transistors with metal gate electrodes

A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

Block Contact Architectures for Nanoscale Channel Transistors

A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

Method for forming field effect transistor having multiple gate electrodes surrounding the channel region

Field effect transistor having multiple gate electrodes surrounding the channel region

A lateral insulating gate type field effect transistor can be manufactured with ease reliably by using a semiconductor substrate having excellent crystal property. A projected portion (2) is formed on a first major surface side of a semiconductor substrate (1). A first gate portion (3) having a width (length) smaller than that of the projected portion (2) is formed on the projected portion (2). An insulating layer (4) is formed on the whole surface of the semiconductor substrate (1) so as to bury the first gate portion (3). The semiconductor substrate (1) is removed horizontally from its second major surface side, i.e., from the opposite side of the side of the projected portion (2) to a position (a) at which the insulating layer (4) is formed so as to bury the projected portion (2) is exposed. A second gate portion (5) is formed on such exposed surface.

Method of manufacturing a lateral field effect transistor

A memory cell with a stored charge on its gate comprising; (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, (E) a first non-linear resistance element having two ends, one end being connected to the first gate, and (F) a second non-linear resistance element composed of the first gate, the insulation layer and either the channel-forming region and at least one of the source/drain regions.

Memory cell with stored charge on its gate and a resistance element having non-linear resistance elements

PROBLEM TO BE SOLVED: To suppress significant increase of cell area by connecting one of two ends of a first nonlinear resistive element with a first gate part and constituting a second nonlinear resistive element of the first gate part, an insulation film, and a channel forming region or one source-drain region. SOLUTION: A first gate part 13 is provided oppositely to a channel forming region 15 through an insulation film 12. The first gate part 13 is coupled capacitively with a second gate part 19 and source-drain regions 16, 17 are provided contiguously to the channel forming region 15 while spaced apart from each other. The first gate part 13 is connected with one end of the first nonlinear resistive element 30 having the other end connected with a bit line BL. A second nonlinear resistive element 33 is composed of the first gate part 13, the insulation film 12, and the channel forming region 15 or one source-drain region 16, 17 thus suppressing significant increase of cell area.

Mikio Mukai

Papers

Method for forming field effect transistor having multiple gate electrodes surrounding the channel region

Field effect transistor having multiple gate electrodes surrounding the channel region

Method of manufacturing a lateral field effect transistor

Memory cell with stored charge on its gate and a resistance element having non-linear resistance elements

Gate charge storage type memory cells