A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

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3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

A system, method, and article of manufacture are provided for obtaining information on a mobile computing environment utilizing a distributed communication network. A pattern template is generated. This pattern template is stored on a thin client computer. A query is then created on the thin client computer based in part on user input. A network is queried for information utilizing a distributed communication network. A response is then received to the query from the distributed communication network. This response is processed utilizing an application tool on the thin client computer. The response is filtered by the application tool based on the pattern template. Information is then displayed to a user.

A system, method and article of manufacture for a mobile communication network utilizing a distributed communication network

A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures.

Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process

A shower head of a metal CVD apparatus has a raw gas passage and a reduction gas passage for independently and respectively supplying a raw gas and a reduction gas into a process chamber. The shower head includes upper, middle and lower blocks which are formed independently of each other. Each of the raw gas passage and the reduction gas passage is branched from the upper block to the lower block. A coolant passage is formed in the lower block near supply outlets of the raw gas and the reduction gas for cooling the supply outlets. A heater is arranged in the upper and middle blocks for heating the raw gas passage.

Shower head and film forming apparatus using the same

A plasma CVD apparatus for forming a deposited film on a base body by introducing a gas of a compound into a chamber and converting the gas into plasma by applying a high frequency electric power, includes a gas feeding pipe leading from the exterior of the chamber into the interior of the chamber, and a heating device. The heating device heats at least a part of the gas feeding pipe inside the chamber, thereby preventing the gas from condensing or solidifying. With this apparatus, plasma CVD can stably be carried out using gases of various compounds which are liquid or solid at room temperature.

Apparatus for plasma chemical vapour deposition

A plasma chemical vapor deposition method for forming a film on a substrate which is placed on one of a pair of electrodes oppositely arranged within the reaction chamber of a reactor. A plurality of power generators of different frequencies are applied to the electrodes to excite reactive gases introduced into the reaction chamber, whereby the reactive gases are transformed into a plasma and a desired film is formed on the substrate. Film with a small number of pinholes was formed at a relatively high deposition rate by combinations of power generator frequencies of, for example, 13.56 MHz and 1 MHz, 13.56 MHz and 50 KHz, and 5 MHz and 400 KHz.

Vapor phase growth method

A three-dimensional (3-D) CMOS integrated circuit with a structure, in which one type of transistor is fabricated directly above a transistor of the opposite type with separate gates and an insulator in between, has successfully been fabricated by using laser beam recrystallization. Seven-stage ring oscillators fabricated in the 3-D structure have a propagation delay of 8.2 ns. In the present experiment, a double-layer of silicon-nitride and phospho-silicate-glass (PSG) film has been used as an intermediate insulating layer between the top and the bottom devices. This CMOS structure and the process technology we have developed here can be the basis for realizing a multilayered 3-D device composed of vertically stacked transistors with separate gates and an insulating layer in between.

Three-dimensional CMOS IC's Fabricated by using beam recrystallization

A method of plasma enhanced chemical vapor deposition of a phosphosilicate glass film on a substrate from a reaction gas mixture including SiH4, N2 O and PH3 is disclosed. This deposition is effected under the conditions such that a mol ratio of N2 O to SiH4 (N2 O/SiH4) in the reaction gas mixture is 50 or more and that a mol ratio of PH3 to SiH4 (PH3 /SiH4) in the reaction gas mixture is 0.08 or less. In the phosphosilicate glass film thus deposited, no cracking occurs due to a high temperature heat-treatment and due to the stress, caused by cooling the deposited films to an ordinarily ambient temperature.

Method of plasma enhanced chemical vapor deposition of phosphosilicate glass film

A silicon nitride film containing from 20 to 70% oxygen, for use as a surface passivation film, has enhanced ultraviolet ray transmissivity while exhibiting the desirable moisture proofness quality of a silicon nitride film.

Mikio Takagi

Papers

Apparatus for plasma chemical vapour deposition

Vapor phase growth method

Three-dimensional CMOS IC's Fabricated by using beam recrystallization

Method of plasma enhanced chemical vapor deposition of phosphosilicate glass film

UV erasable EPROM with UV transparent silicon oxynitride coating