In this paper we propose a UML/MDA approach, called MoPCoM methodology, to design high quality real-time embedded systems. We have defined a set of rules to build UML models for embedded systems, from which VHDL code is automatically generated by means of MDA techniques. We use the MARTE profile as an UML extension to describe real-time properties and perform platform modeling. The MoPCoM methodology defines three abstraction levels: abstract, execution and detailed modeling levels (AML, EML and DML, respectively). We detail the lowest MoPCoM level, DML, design rules in order to perform automatically VHDL code generation. A viterbi coder has been used as a first case study.

/pdf/a-co-design-approach-for-embedded-system-modeling-and-code-2i2jz9jsax.pdf

A co-design approach for embedded system modeling and code generation with UML and MARTE

MARTE profile extension for modeling dynamic power management of embedded systems

The technique of using workload dependent dynamic power management (i.e., variable power and speed of processor cores according to the current workload) to improve system performance and to reduce energy consumption is investigated. Typically, the power supply and the core speed are increased when there are more tasks in a server, such that tasks can be processed faster and the average task response time is reduced. On the other hand, the power supply and the core speed are decreased when there are less tasks in a server, such that energy consumption can be reduced without significant performance degradation. A queueing model of multicore server processors with workload dependent dynamic power management is established. Several speed schemes are proposed and it is demonstrated that for the same average power consumption, it is possible to design a multicore server processor with workload dependent dynamic power management, such that its average task response time is shorter than a multicore server processor of constant speed (i.e., without workload dependent dynamic power management). It is shown that given certain application environment and average power consumption, there is an optimal speed scheme that minimizes the average task response time. For two-speed schemes, the problem of optimal design of a two-speed scheme for given power supply and power consumption model is formulated and solved. It is pointed out that power consumption reduction subject to performance constraints can be studied in a similar way as performance improvement (i.e., average task response time reduction) subject to power consumption constraints. To the best of our knowledge, this is the first work on analytical study of workload dependent dynamic power management.

http://www.cs.newpaltz.edu/~lik/publications/Keqin-Li-IEEE-TCC-2016.pdf

Improving Multicore Server Performance and Reducing Energy Consumption by Workload Dependent Dynamic Power Management

Signal processing algorithms become more and more complex and the algorithm architecture adaptation and design processes cannot any longer rely only on the intuition of the designers to build efficient systems. Specific tools and methods are needed to cope with the increasing complexity of both algorithms and platforms. This paper presents a new framework which allows the specification, design, simulation and implementation of a system operating at a higher level of abstraction compared to current approaches. The framework is base on the usage of a new actor/dataflow oriented language called CAL. Such language has been specifically designed for modelling complex signal processing systems. CAL data flow models expose the intrinsic concurrency of the algorithms by employing the notions of actor programming and dataflow. Concurrency and parallelism are very important aspects of embedded system design as we enter in the multicore era. The design framework is composed by a simulation platform and by Cal2C and CAL2HDL code generators. This paper described in details the principles on which such code generators are based and shows how efficient software (C) and hardware (VHDL and Verilog) code can be generated by appropriate CAL models. Results on a real design case, a MPEG-4 Simple Profile decoder, show that systems obtained with the hardware code generator outperform the hand written VHDL version both in terms of performance and resource usage. Concerning the C code generator results, the results show that the synthesized C-software mapped on a SystemC scheduler platform, is much faster than the simulated CAL dataflow program and approaches handwritten C versions.

https://hal.archives-ouvertes.fr/hal-00336520/document

Dataflow/Actor-Oriented language for the design of complex signal processing systems

A method, information processing system, and computer readable storage medium are provided for dynamically managing accelerator resources. A first set of hardware accelerator resources (122) is initially assigned to a first information processing system (104), and a second set of hardware accelerator resources (124) is initially assigned to a second information processing system (106). Jobs running on the first and second information processing systems (116, 118) are monitored (132). When one of the jobs fails to satisfy a goal, at least one hardware accelerator resource in the second set of hardware accelerator resources from the second information processing system are dynamically reassigned (138) to the first information processing system.

Goal oriented performance management of workload utilizing accelerators

Disclosed are additives which are useful as dispersants in lubricating oils, gasolines, marine crankcase oils and hydraulic oils. In particular, disclosed are multiply adducted alkenyl or alkyl succinimides which contain carbamate functionalities.

Modeling Embedded Software Platforms with a UML Profile.

This case study presents UML-based design and implementation of a wireless video terminal on a multiprocessor system-on-chip (SoC). The terminal comprises video encoder and WLAN communications subsystems. In this paper, we present the UML models used in designing the functionality of the subsystems as well as the architecture of the terminal hardware. We use the Koski design flow and tools for fully automated implementation of the terminal on FPGA. Measurements were performed to evaluate the performance of the FPGA implementation. Currently, fully software encoder achieves the frame rate of 3.0 fps with three 50MHz processors, which is one half of a reference C implementation. Thus, using UML and design automation reduces the performance, but we argue that this is highly accepted as we gain significant improvement in design efficiency and flexibility. The experiments with the UML-based design flow proved its suitability and competence in designing complex embedded multimedia terminals.

https://link.springer.com/content/pdf/10.1155%2F2007%2F85029.pdf

Implementing a WLAN video terminal using UML and fully automated design flow

The paper presents a novel scheme of dynamic power management for UML modeled applications that are executed
on a multiprocessor System-on-Chip (SoC) in a distributed manner. The UML models for both application
and architecture are designed according to a well-defined UML profile for embedded system design, called TUT-Profile.
Application processes are considered as elementary units of distributed execution, and their mapping on
a multiprocessor SoC can be dynamically changed at run-time. Our approach on the dynamic power management
balances utilized processor resources against current workload at runtime by (1) observing the processor
and workload statistics, (2) re-evaluating the amount of required resources (i.e. the number of active processors),
and (3) re-mapping the application processes to the minimum set of active processors. The inactive processors
are set to a power-save state by using clock-gating. The approach integrates the well-known power management
techniques tightly with the UML based design of embedded systems in a novel way. We evaluated the dynamic
power management with a WLAN terminal implemented on a multiprocessor SoC on Altera Stratix II FPGA
containing up to five Nios II processors and dedicated hardware accelerators. Measurements proved up to 21%
savings in the power consumption of the whole FPGA board.

Dynamic power management for UML modeled applications on multiprocessor SoC

This paper presents automated distribution of embedded real-time applications modeled in Unified Modeling Language version 2.0 (UML 2.0). The automated distribution requires methods and tools for design automation, as well as the run-time environment for the distributed execution on the target platform. Executable application code is generated from UML models, and UML with a custom profile is used to abstract hardware architecture and configure application mapping. For experimenting, a full featured WLAN terminal was designed in UML and implemented as a distributed multiprocessor system-on-chip (SoC) on an FPGA prototype platform. Measurements show that a 50-70% reduction in protocol delays is achived with distribution, and delay variations are reduced 45-85%.

Mikko Setälä

Papers

Modeling Embedded Software Platforms with a UML Profile.

Implementing a WLAN video terminal using UML and fully automated design flow

Dynamic power management for UML modeled applications on multiprocessor SoC

Automated distribution of UML 2.0 designed applications to a configurable multiprocessor platform

Automated distribution of UML 2.0 designed applications to a configurable multiprocessor platform