Intellectual property protection (IPP) of hardware designs is the most important requirement for many Field Programmable Gate Array (FPGA) intellectual property (IP) vendors. Digital watermarking has become an innovative technology for IPP in recent years. Existing watermarking techniques have successfully embedded watermark into IP cores. However, many of these techniques share two specific weaknesses: 1) They have extra overhead, and are likely to degrade performance of design; 2) vulnerability to removing attacks. We propose a novel watermarking technique to watermark FPGA bitfile for addressing these weaknesses. Experimental results and analysis show that the proposed technique incurs zero overhead and it is robust against removing attacks.

Watermarking FPGA Bitfile for Intellectual Property Protection

Watermarking techniques were introduced into the process of IC design to provide confident proofs of the copyright. Due to the difficulty of applying traditional constraint-based watermarking techniques, we propose a new watermarking method for soft IP core copyright protection, which we called the detector-based technique. In this new approach, the watermarking detector plays an important role. Since the detector transfers the difficulty of solving NP-hard problems in traditional constraint-based approaches to the problem of managing a vast sum of detector data, which concerns mainly well-grounded database theory, our detector-based technique presents a practical support for the industrialization of an IP-reuse platform, on which the copyright issues rely not only on legal means, but also design data itself. We also analyze the feasibility of our detector-based watermarking technique in the last part of the paper.

Detector-based watermarking technique for soft IP core protection in high synthesis design level

A Chaotic IP Watermarking in Physical Layout Level Based on FPGA

This paper describes a design approach for incorporating sequence-aware watermarks in soft intellectual property (IP) embedded processors. The influence of watermark sequence parameters on detection, area, and power overheads is examined, and consequently a method for incorporating sequence-aware watermarks in soft IP embedded processors is proposed. The intrinsic parameters of sequences, such as the activity factor and the overlapping factor, are introduced, and their impact on correlation results is demonstrated. Measurement and application-specified integrated circuits validate the design approach and demonstrate the resulting IP protection and subsequent costs for constrained embedded processors. Results presented in this paper show that the tradeoff occurs between the watermark robustness against third-party IP attacks and hardware implementation costs. The analysis of this tradeoff is provided, and an application specific watermark implementation is proposed.

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Sequence-Aware Watermark Design for Soft IP Embedded Processors

The Design and FPGA Implementation of FSM-based Intellectual Property Watermark Algorithm at Behavioral Level

A new watermarking method for hard IP core copyright protection in physical layout design level based on the constraint concept is presented. It can apply to both VLSI design IP core and full-custom design IP core. The principle is proposed and the watermarking design flow using commercial EDA design tools is discussed. The experiment method to validation our approach is also included in this paper.

Min Ni

Papers

Constraint-based watermarking technique for hard IP core protection in physical layout design level