Bilayer graphene like monolayer graphene has a zero bandgap. To use as a channel material of FETs, its band gap should be open which is crucial for its application in logic circuits. Several methods have been developed to open the band gap in graphene. The simple way is cutting graphene into ribbons. In this paper, a novel structure for a dual-gated bilayer graphene nanoribbon field-effect transistor (BLGNRFET) is suggested, which merges the advantages of high and low dielectric constants. The gate insulator of FET is divided into four parts with different dielectric materials, so the proposed device is called FDI-BLGNRFET. All of the possible state of gate insulators which can happen for these four different parts are surveyed. The simulations are conducted by means of the self-consistent solution of the Poisson and Schrodinger equations within the Non- Equilibrium Green Function (NEGF) and a tight-binding Hamiltonian, in the real space approach. Regarding to the results, for the proposed FDI-BLGNRFET with K1 = K2 = 25 and K3 = K4 = 3.9, the maximum ${I_{ON}}/{I_{OFF}}$ ratio 119% higher than the conventional BLGNRFET is achieved which is still remains inadequate for getting an acceptable $({{I_{ON}}/{I_{OFF}}})$ ratio in CMOS performance.

A Functional Study of a Bilayer Graphene Nanoribbon FET With Four Different Gate Insulators

http://scientiairanica.sharif.edu/article_4139_9698ec79273993c1fa416aa9c152ff4d.pdf

On the oscillatory frequency of the carbon nanotube-based nanothermometers

Seven Strategies to Suppress the Ambipolar Behaviour in CNTFETs: a Review

http://scientiairanica.sharif.edu/article_3467_f578a056accf3ed14507b4a2428b1109.pdf

Simulation of Carbon Nanotube Field Effect Transistor with Two Different Gate Insulator

In this paper a low swing driver-receiver pair (lhos-lp) for driving signals is proposed to optimize the energy dissipation and delay of global interconnect lines. The simulation, performed based on 1V 0.13µm CMOS technology with HSPICE, for signal transmission along a wire- length of 10 mm. The simulation results show lhos-lp is 18% and 14% better than other similar signaling schemes (lhos-db and lhos-lhos) and consumes 17% lower energy than lhos-lhos and it has similar energy consumption respect to lhos-lp. Also this circuit performs 28% and 20% better than lhos-lhos and lhos-db in a point of energy delay product.

Mina Fallah

Papers

Simulation of Carbon Nanotube Field Effect Transistor with Two Different Gate Insulator

An optimized low swing CMOS driver-receiver for on-chip interconnects