Design of low power approximate floating‐point adders

Approximate computing has emerged as an efficient solution for energy saving at the expense of calculation accuracy, especially for floating-point operation intensive applications, which have urgent demands for some uniform design frameworks for floating-point approximate computing combining the approximate computing techniques with the metrics of applications. In this paper, a simple approximate method with a zero-mean noise for the mantissa was introduced firstly, called PAM. Secondly, based on the proposed approximate method, the corresponding noise propagation models for floating-point operations were built, including floating-point addition, subtraction, and multiplication. Thirdly, a uniform design framework, which is only related to the operational-level topology of applications, was presented. The presented design framework can be used to evaluate the quality of data produced by applications before the circuit design is completed, and the efficient bit width of the mantissa can be obtained under specific requirements, which is also suitable for truncation. Finally, we studied the feasibility of the proposed design framework through two typical applications of image processing, edge detection and Gaussian filtering. The experimental results of edge detection have shown that our proposed design framework could effectively predict efficient bit width under the specific peak signal-to-noise ratio, with a difference of 1–2 bits in extreme situations. The Gaussian filtering experiment has demonstrated that the proposed design framework could apply to applications with complex calculations and structures.

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Metrics, Noise Propagation Models, and Design Framework for Floating-Point Approximate Computing

Due to the high demands for computing, the available resources always lack. The approximate computing technique is the key to lowering hardware complexity and improving energy efficiency and performance. However, it is a challenge to properly design approximate multipliers since input data are unseen to users. This challenge can be overcome by Machine Learning (ML) classifiers. ML classifiers can predict the detailed feature of upcoming input data. Previous approximate multipliers are designed using simple adders based on ML classifiers but by using a simple adder-based approximate multiplier, the level of approximation cannot change at runtime. To overcome this drawback, using an accumulator and reconfigurable adders instead of simple adders are proposed in this paper. Also, the rounding technique is applied to approximate floating-point multipliers for further improvement. Our experimental results show that when the error tolerance of our target application is less than 5%, the proposed approximate multiplier can save area by 70.98%, and when the error tolerance is less than 3%, a rounding enhanced simple adders-based approximate multiplier can save area by 65.9% and a reconfigurable adder-based approximate multiplier with rounding can reduce the average delay and energy by 54.95% and 46.67% respectively compared to an exact multiplier.

A Reconfigurable Approximate Floating-Point Multiplier with kNN

Memristor-based crossbar architectures have been explored by researchers for neuromorphic computing, where analog vector-matrix multiplication can be carried out in a single time step. In this paper we explore such architectures for carrying out various arithmetic operations. Since the computations are carried out in analog domain, they are affected by fabrication and performance variability of the manufactured devices. As a result, there can be inherent errors during the computation. However, the architecture can be suitable for approximate computing applications where some errors can be tolerated. We have proposed a method for carrying out arithmetic operations with any multiple of k-bit resolution on the crossbar, for some limited values of k. The fault tolerant capability of the proposed architecture is evaluated through experimentation on benchmark datasets. We also perform case studies to analyze the performance of the approach with particular emphasis on approximate computing. The results of the case studies show that certain applications indeed exhibit fault tolerance in presence of faulty memristors. 

Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications

Memristor-based crossbar architectures have been explored by researchers for neuromorphic computing, where analog vector-matrix multiplication can be carried out in a single time step. In this paper we explore such architectures for carrying out various arithmetic operations. Since the computations are carried out in analog domain, they are affected by fabrication and performance variability of the manufactured devices. As a result, there can be inherent errors during the computation. However, the architecture can be suitable for approximate computing applications where some errors can be tolerated. We have proposed a method for carrying out arithmetic operations with any multiple of k-bit resolution on the crossbar, for some limited values of k. The fault tolerant capability of the proposed architecture is evaluated through experimentation on benchmark datasets. We also perform case studies to analyze the performance of the approach with particular emphasis on approximate computing. The results of the case studies show that certain applications indeed exhibit fault tolerance in presence of faulty memristors.

In many real computations such as arithmetic operations in hidden layers of a neural network, some amounts of inaccuracies can be tolerated without degrading the final results (e.g., maintaining the same level of accuracy for image classification). This paper presents design of kNN-CAM, a k-Nearest Neighbors (kNN)-based Configurable Approximate floating point Multiplier. kNN-CAM utilizes approximate computing opportunities to deliver significant area and energy savings. A kNN engine is trained on a sufficiently large set of input data to learn the quantity of bit truncation that can be performed in each floating point input with the goal of minimizing energy and area. Next, this trained engine is used to predict the level of approximation for unseen data. Experimental results show that kNN-CAM provides about 67% area saving and 19% speedup while losing only 4.86% accuracy when compared to a 100% accurate multiplier. Furthermore, the application of kNN-CAM in implementation of a handwritten digit recognition provides 47.2% area saving while the accuracy is dropped by only 0.3%.

Ming Yan

Papers

kNN-CAM: A k-Nearest Neighbors-based Configurable Approximate Floating Point Multiplier