: Recently several architectural approaches have been explored that promise to hide memory latency for applications that include data-intensive applications while improving scalability The SLIIC project demonstrated and compared some of the advantages and disadvantages of the PIM (processor-in-memory) and stream processing approaches to hiding memory latency. The SLIIC project built board prototypes for PIM and stream processing architectures and implemented data-intensive applications in simulation and in hardware to measure the performance. Speedups of up to 54 measured in cycles and 16 measured in execution time were obtained over commercial microprocessors.

http://www.dtic.mil/dtic/tr/fulltext/u2/a429293.pdf

SLIIC: System-Level Intelligent Intensive Computing

∗ Effort sponsored by Defense Advanced Research Projects Agency (DARPA) through the Air Force Research Laboratory, USAF, under agreement number F30602-99-1-0521. The U.S. Government is authorized to reproduce and distribute reprints for governmental purposes notwithstanding any copyright annotation thereon. The views and conclusions contained herein are those of the authors and should not interpreted as necessarily representing the official policies or endorsement, either expressed or implied, of the Defense Advanced Research Projects Agency (DARPA), Air Force Research Laboratory, or the U.S. Government. † Richard Chau was working for Lockheed martin when this work was conducted. Abstract

Implementations of real-time data intensive applications on PIM-based multiprocessor systems

The growing gap in performance between processor and memory speeds has created a problem for data-intensive applications. A recent approach for solving this problem is to use processor-in-memory (PIM) technology. PIM technology integrates a processor on a DRAM memory chip, which increases bandwidth between the processor and memory. In this paper, we discuss two PIM-based multiprocessor systems, the System Level Intelligent Intensive Computing (SLIIC) Quick Look (QL) board and a hypothetical V-IRAM multiprocessor board. The former system includes eight COTS PIM chips that are connected by a flexible FPGAbased interconnect network. The V-IRAM board modeled contains four Berkeley V-IRAM PIM processors (currently under development) that are connected using FPGAs. The performance of several data intensive applications on the SLIIC QL board is measured. The performance of the applications on the V-IRAM board is modeled at the clock cycle level. The performances of these boards are compared with a PowerPC-based multicomputer and a Pentium system.

http://ieeexplore.ieee.org/iel5/7373/20001/00925063.pdf

Ming Zhu

Papers

Implementations of real-time data intensive applications on PIM-based multiprocessor systems

Implementations of Real-time Data Intensive Applications on PIM-based