In a semiconductor device including a semiconductor substrate (1, 1'), an insulating layer (2) formed on the semiconductor substrate and a semiconductor layer (3) formed on the insulating layer, the impurity concentration of at least one part of the semiconductor substrate in the proximity of the insulating layer is rich, i.e., higher than that of the other part of the semiconductor substrate.

SOI-type semiconductor device with suppressed spread of depletion region

In this overview, the low-frequency noise behaviour of devices fabricated in silicon-on-insulator technologies is described. The different potential noise sources are analysed and illustrated by experimental results, mainly obtained on MOSFETs. Some SOI-specific noise behaviour is highlighted, as for instance the kink-related excess low-frequency noise overshoot. It is shown furthermore that SOI MOSFETs suffer from so-called random telegraph signals, which can originate from the front- or the back-gate dielectric, or from defects located in the thin Si active layer. The impact of the substrate type (SIMOX, bonded, ZMR,…) is discussed. At the same time, it is shown that the used technology and device structure can have a pronounced effect on the LF noise performance. Finally, the response of SOI MOSFETs on ionizing radiation (γs, X-rays,…) is studied through the LF noise degradation, in view of radiation-hardened applications.

The low-frequency noise behaviour of silicon-on-insulator technologies

This work investigates and demonstrates the potential of Silicon-On-Insulator (SOI) MOSFETs for high-temperature analog and digital applications. The small area of junctions in SOI/MOS devices reduces the high-temperature leakage currents by as much as 3 to 4 orders of magnitude over regular (bulk) MOS devices. The threshold voltage variation with temperature is 2 to 3 times smaller than in bulk devices, and the output conductance of SOI MOSFETs actually improves as temperature is increased. These properties enable the fabrication of digital and analog SOI/CMOS circuits operating up to over 300 degrees C with little performance degradation. This paper describes the high-temperature performances of small SOI/CMOS circuit blocks such as static and dynamic logic gates, frequency dividers, and operational amplifiers. >

SOI technology for high-temperature applications

An overview is given on the low-frequency (LF) noise of silicon-on-insulator (SOI) devices and technologies. In the first two parts, noise mechanisms specific for SOI are discussed, namely, the front–back-gate coupling in fully-depleted MOSFETs and the Lorentzian noise overshoot in floating-body operating transistors. In the next part, the impact of the technology (SOI substrate, gate stack processing, isolation module, …) on the LF noise is described. From this, it is derived that scaling below the 0.25 μm CMOS node did not result in the anticipated reduction of the 1/f noise with tfox or t fox 2 . This is related to the increasing amount of nitrogen incorporated in the thin SiON front gate oxides with thickness tfox. In the case of high-κ dielectrics it is frequently observed that these have a higher trap density compared to SiO2. On the other hand, today’s multigate SOI transistors seem to give rise to similar gate oxide trap densities and hence, 1/f noise, than their single-gate counterparts. In the last part, operational and circuit aspects will be discussed, which might have a beneficial impact on the LF noise performance.

Low-frequency noise in silicon-on-insulator devices and technologies

This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistors connected in series with gates shortened, acting as a single device. The doping concentration of the two transistors in the structure is different, leading to higher threshold voltage of the transistor at the source side of the composite structure than that of the transistor at the drain side. By reducing the doping concentration level at the channel of the transistor at drain side of the composite structure, forcing it to work in saturation, part of the applied drain bias is absorbed and does not reach the transistor close to the source, which is the main responsible for the overall device characteristics. As a result, larger drain current level and transconductance are obtained in comparison to symmetric self-cascode (where both transistors present same doping level) apart from promoting output conductance reduction. The transconductance, output conductance, Early voltage, and intrinsic voltage gain are used as figures of merit to demonstrate and validate the advantages of the proposed structure. The influence of channel length and doping concentration are also evaluated. The A-SC configuration is fully compatible with any standard FD SOI MOSFET technology with multiple threshold voltages. A simulation analysis demonstrates the feasibility of the proposed asymmetric structure in a UTBB FD SOI technology.

On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

A twin-MOSFET structure is proposed for suppression of the kink and parasitic bipolar effects in SOI MOS transistors. It is also an attractive candidate to provide satisfactory linear device operation at liquid He temperature. The device consists of two transistors in series with a common gate but it operates as a single transistor. Kink effect can be confined to the one “slave” transistor while the other “master” transistor can be kept free from the kink effect. If the gate length of the master transistor is larger than that of the slave one, the kink-free master transistor dominates the overall output characteristics of the device. As a consequence, the kink effect is suppressed in the overall output characteristics of the device. Furthermore, the parasitic bipolar effect in SOI MOSFETs is also significantly reduced and the saturation drain output impedance as well as the output breakdown characteristics are drastically improved. Kink-free and very flat output characteristics are obtained at both room and liquid He (4.2 K) temperatures.

Minghui Gao

Papers

Twin-MOSFET structure for suppression of kink and parasitic bipolar effects in SOI MOSFETs at room and liquid helium temperatures