A method of testing a semiconductor structure such as a finished or part-finished semiconductor wafer, a die on such a wafer, part of such a die, or even one functional element (e.g. a transistor or memory cell) of such a die. The method includes the steps of charging at least a part of the semiconductor structure; applying an electric field perpendicular to a surface of the structure while charging so as to determine charging potential and polarity (i.e. charging either positively or negatively); interrogating the structure including the charged part with a charged particle beam, such as an electron beam, so as to obtain voltage contrast data for the structure; and analyzing the data to determine the functionality of the element. Apparatus according to the invention for testing semiconductor structures, includes: a system for applying charge to at least part of the semiconductor structure, such as an electron beam, flood gun or mechanical probe; an electric field generator, typically an electrode spaced from the surface of the structure, which applies an electric field perpendicular to a surface of the structure so as to determine the potential and polarity of the charge applied to the element (i.e. positive or negative charge); a charged particle beam device such as an electron beam for interrogating the charged element; and a detector such as a secondary electron detector which obtains voltage contrast data from the structure on interrogation with the charged particle beam.

Methods and apparatus for testing semiconductor and integrated circuit structures

One embodiment of the present invention is a method of detecting defects in a patterned substrate, including: (a) positioning a charged-particle-beam optical column relative to a patterned substrate, the charged-particle-beam optical column having a field of view (FOV) with a substantially uniform resolution over the FOV; (b) operating the charged-particle-beam optical column to acquire images of a region of the patterned substrate lying within the FOV by scanning the charged-particle beam over the patterned substrate; and (c) comparing the acquired images to a reference to identify defects in the patterned substrate.

Detection of defects in patterned substrates

An electron beam addressable memory is disclosed in which information is stored as an electric charge in a multilayered memory target The multilayered memory comprises a conductive layer, an insulating layer having a plurality of charge storage sites, a layer of n-type and a layer of p-type semiconductor material having a p-n junction therebetween The method of writing causes charge to be stored at selected sites in the insulating layer The method of reading causes the current through the p-n junction, which is reverse biased, to vary in magnitude depending upon whether or not the beam impinges on a charged site The read and write electron beams are preferably of the same energy and a different voltage is applied to the conductive layer during reading than is applied during writing In another embodiment, the conducting layer is omitted and the effect of different voltages applied to the conducting layer is produced by secondary emission from the insulating layer

Method and apparatus for storing and reading out charge in an insulating layer

A method for electrically testing a wafer that includes: receiving a wafer having a first layer that is at least partly conductive and a second layer formed over the first layer, following production of openings in the second layer; directing towards the wafer a first set of beams of charged particles that are oriented at a first set of angles in relation to the wafer, wherein each angle of the first set of angles deviates substantially from normal, so as to pre-charge an area of the second layer without substantially pre-charging the first layer; scanning the area of the wafer by a second set of beams of charged particles that are oriented at a second set of angles in relation to the wafer, and collecting charged particles scattered from the area wafer. A system for electrically testing a semiconductor wafer, the system including: at least one charged particle beam source; at least one detector, adapted to collect charged particles scattered from the wafer; wherein the wafer comprises a first layer that is at least partly conductive and a second layer formed over the first layer, following production of openings in the second layer; wherein the system is adapted to: (i) direct towards the wafer a first set of beams of charged particles that are oriented at a first set of angles in relation to the wafer, wherein the first angle deviates substantially from normal, so as to pre-charge an area of the second layer without substantially pre-charging the first layer; (ii) scan the area of the wafer by a second set of beams of charged particles that are oriented at a second set of angles in relation to the wafer, and collect charged particles scattered from the area of the wafer.

Apparatus and method for voltage contrast analysis of a wafer using a tilted pre-charging beam

A ferroelectric space charge capacitor analog memory device includes a pair of spaced first and second electrodes; a ferroelectric dielectric disposed between the electrodes; and a signal source for applying to the dielectric a write signal equal to or greater than the coercive voltage to write the dielectric into a predetermined polarization state in the range from zero to maximum coerced polarization and to establish, proximate the interface between the dielectric and each electrode, a space charge region having a charge opposite to that applied to the electrode, with a neutral region between the space charge regions, the relative sizes of the neutral and space charge regions defining the capacitance of the dielectric, the neutral region having an internal polarization field opposite to that represented by the space charge regions; a bias source for applying to the dielectric a bias voltage less than the coercive voltage at a rate slower than the rate of space charge formation to define the capacitance level representative of the predetermined polarization state; the signal source for introducing to the dielectric a read signal at a rate faster than the rate of space charge formation which together with the bias voltage is less than the coercive voltage; and a current detector responsive to the introduction of the read signal to the dielectric for determining the capacitance level representative of the predetermined polarization state.

Ferroelectric space charge capacitor analog memory

A slow write-fast read out information storage and retrieval method and system is described for use as a computer memory. The method and system employs a memory element comprising a conductive back layer, a semiconductor layer and an insulator enriched with an additive polarizing material such as the alkali metals sodium or lithium and a conductive front layer arranged in the order named in the form of a sandwich with the semiconductor layer and polarizing material enriched insulator layer forming an interface. By selectively heating discrete different locations on the memory element with a directed electron beam in accordance with the intelligence to be recorded, and applying a polarizing electric potential across the memory element which maintains the insulator layer positive with respect to the semiconductor layer concurrently with the selective heating, positive electric charges (which are non-destructive during read-out) will be formed in the insulator layer due to mobile ions of the additive alkali metal polarizing material which are transported to the interface as a result of the polarizing potential. The positive electric charges in turn produce space charge regions in the semiconductor layer adjacent to the interface at the selectively heated different discrete locations. If the semiconductor layer is a p-type semiconductor, the space charge region is a depletion region. If the semiconductor layer is a n-type semiconductor, the space charge region will be an accumulation region. By subsequently allowing the insulator layer to cool, the mobile ion charges thus transported to the interface at the selectively heated locations will be frozen in to thereby form selectively located, semi-permanent, space charge regions in the semiconductor layer whereby the intelligence to be recorded is embodied in the selectively located charges. In a subsequent reading operation, a read-out electron beam is caused to penetrate through the insulator layer and interface to the space charge region of the semiconductor layer where it will produce electron-hole carriers in the space charge region. To facilitate the reading operation, a polarizing, reading potential may be applied across the memory element simultaneously with the readout electron beam. In the selectively located space charge regions, a considerably increased electron-hole pair current will be produced compared to that normally induced by the electron beam itself in those regions which have not been selectively polarized. Consequently a pulsed current output can be derived during the reading operation which is indicative of the data or intelligence stored in the memory element.

Mitchell S Cohen

Papers

Slow write-fast read memory method and system