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Design Of Analog Cmos Integrated Circuits

Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

The volume, veracity, variability, and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability, and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks, and open problems in the field of neuromemristive circuits for edge computing.

Neuromemristive Circuits for Edge Computing: A Review

Approximate computing is a promising design paradigm for better performance and power efficiency. In this paper, we propose a power efficient framework for analog approximate computing with the emerging metal-oxide resistive switching random-access memory (RRAM) devices. A programmable RRAM-based approximate computing unit (RRAM-ACU ) is introduced first to accelerate approximated computation, and an approximate computing framework with scalability is then proposed on top of the RRAM-ACU. In order to program the RRAM-ACU efficiently, we also present a detailed configuration flow, which includes a customized approximator training scheme, an approximator-parameter-to-RRAM-state mapping algorithm, and an RRAM state tuning scheme. Finally, the proposed RRAM-based computing framework is modeled at system level. A predictive compact model is developed to estimate the configuration overhead of RRAM-ACU and help explore the application scenarios of RRAM-based analog approximate computing. The simulation results on a set of diverse benchmarks demonstrate that, compared with a x86–64 CPU at 2 GHz, the RRAM-ACU is able to achieve 4.06– $196.41 {\times }$ speedup and power efficiency of 24.59–567.98 GFLOPS/W with quality loss of 8.72% on average. And the implementation of hierarchical model and X application demonstrates that the proposed RRAM-based approximate computing framework can achieve >12.8 $\times$ power efficiency than its pure digital implementation counterparts (CPU, graphics processing unit, and field- programmable gate arrays).

https://nicsefc.ee.tsinghua.edu.cn/media/publications/2015/IEEE%20TCAD_170.pdf

RRAM-Based Analog Approximate Computing

Nonlinear activation function is one of the main building blocks of artificial neural networks. Hyperbolic tangent and sigmoid are the most used nonlinear activation functions. Accurate implementation of these transfer functions in digital networks faces certain challenges. In this paper, an efficient approximation scheme for hyperbolic tangent function is proposed. The approximation is based on a mathematical analysis considering the maximum allowable error as design parameter. Hardware implementation of the proposed approximation scheme is presented, which shows that the proposed structure compares favorably with previous architectures in terms of area and delay. The proposed structure requires less output bits for the same maximum allowable error when compared to the state-of-the-art. The number of output bits of the activation function determines the bit width of multipliers and adders in the network. Therefore, the proposed activation function results in reduction in area, delay, and power in VLSI implementation of artificial neural networks with hyperbolic tangent activation function.

Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function

An important part of any hardware implementation of artificial neural networks (ANNs) is realization of the activation function which serves as the output stage of each layer. In this work, a new NMOS/PMOS design is proposed for realizing the sigmoid function as the activation function. Transistors in the proposed neuron are biased using only one biasing voltage. By operating in both triode and saturation regions, the proposed neuron can provide an accurate approximation of the sigmoid function. The neuron circuit is designed and laid out in 90-nm CMOS technology. The proposed neuron can be potentially used in implementation of both analog and hybrid ANNs.

Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron

Sigmoid and Hyperbolic Tangent are widely used as activation functions in artificial neural networks. Exponential term and division are basic building blocks of these functions. This paper proposes precise and efficient hardware implementations for sigmoid and hyperbolic tangent functions using exponential function approximation. Performance of both functions has been verified which shows that the proposed implementations have up to 99.97% similarity with the ideal transfer functions while the circuits take maximum 2% of logic resources when implemented on a Vertex IV FPGA.

Precise digital implementations of hyperbolic tanh and sigmoid function

Optical Character Recognition system (OCR) can be used in intelligent transportation systems for license plate detection. However, most times the systems are unable to work with noisy and imperfect images. In this work, a robust FPGA-based OCR system has been designed and tested with imperfect and noisy license plate images. The OCR system is based on a feedforward neural networks, which uses an efficient and precise neuron. The neuron transfer function is based on an approximation of the Hyperbolic Tangent Activation Function. The neuron is utilized in a 189 − 160 − 36 feed forward neural network configuration. The network parameters were optimized and then tested with noisy images of license plates numbers. The network was able to maintain a 98.2% accuracy in recognizing the characters despite the image imperfections.

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An efficient FPGA implementation of Optical Character Recognition for License Plate Recognition

In this paper, the design and implementation of an analog sigmoid neuron is presented. The activation function of the proposed neuron is implemented based on the piecewise linear approximation in the analog domain. The proposed neuron provides the required accuracy that cannot be achieved in general by analog neural network implementations. General digital outputs of a sigmoid neuron are replaced with fewer analog digits of the continuous valued number system (CVNS), while at the same time maximum approximation error is kept the same as the digital architectures. The proposed CVNS neuron resulted in an optimal ASIC implementation and is suitable for neurochips with on-chip learning. The VLSI implementation of the neuron is carried out using current-mode circuits. The implementation results compare favorably with previously developed structures in terms of area, delay, and power consumption. The proposed neuron structure occupies 28% less area compared with the state-of-the-art methods and it has two times lower power $\times $ delay.

Mitra Mirhassani

Papers

Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function

Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron

Precise digital implementations of hyperbolic tanh and sigmoid function

An efficient FPGA implementation of Optical Character Recognition for License Plate Recognition

An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips