An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Disclosed is a light-emitting diode package, comprising: a package body having a cavity; a light-emitting diode chip having a plurality of light-emitting cells connected in serial with each other; a fluorescent body for converting the wavelength of light emitted by the light-emitting diode chip; and a pair of lead electrodes. The light-emitting cells are connected together in series between the pair of lead electrodes.

Light emitting diode package

A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc. and the passive component such as a chip resistor, a chip capacitor, etc. in the internal portion of the substrate; and simply producing a multilayer wiring structure.

Component built-in module and method for producing the same

A first level packaging wafer (110) is made of a semiconductor or insulating material. The bumps (150B) on the wafer (110) are made using vertical integration technology, without solder or electroplating. More particularly, vias (160) are etched part way into a first surface of the substrate (140). Metal (150) is deposited into the vias (160). Then the substrate (140) is blanket-etched from the back side (110B) until the metal (150) is exposed and protrudes from the vias (160) to form suitable bumps (150B). Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.

Packaging of integrated circuits and vertical integration

A light-emitting device package including: a package main body including a cavity and a lead frame including a mounting portion disposed in the cavity and a plurality of terminal portions; a light-emitting device chip mounted on the mounting portion; a plurality of bonding wires for electrically connecting the plurality of terminal portions and the light-emitting device chip; a light-transmitting encapsulation layer filled in the cavity; and a light-transmitting cap member disposed in the cavity and blocking the encapsulation layer to contact the plurality of bonding wires.

Light emitting device package

An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.

Electronic parts packaging structure and method of manufacturing the same

A process for making a chip sized semiconductor device, in which a semiconductor chip is prepared so as to have electrodes on one of surfaces thereof and an electrically insulating passivation film formed on the one surface except for areas where the electrodes exist. An insulation sheet is prepared so as to have first and second surfaces and a metallic film coated on the first surface. The second surface of the insulation sheet is adhered on the one surface of the semiconductor chip. First via-holes are provided in the metallic film at positions corresponding to the electrodes. Second via-holes are provided in the insulation sheet at positions corresponding to the first via-holes so that the electrodes are exposed. The metallic film is electrically connected to the electrodes of the semiconductor chip through the first and second via-holes. A circuit pattern is formed from the metallic film so that the circuit pattern has external terminal connecting portions. An insulation film is adhered on the insulation sheet so that the external terminal connecting portions are exposed. External connecting terminals are electrically connected to the external terminal connecting portions of the circuit pattern.

Semiconductor device having an element with circuit pattern thereon

In order to achieve high density and high performance package, through silicon vias (TSVs) technology has been desired. Our purpose is the development of silicon interposer which has TSVs and fine multilayer Cu wiring on both side. Since silicon substrate has a quite flat and smooth surface, it can be expected to form fine wiring such as global layer of device. Furthermore, silicon interposer can be expected to show high reliability of bump connection for the reason of the same coefficient of thermal expansion (CTE) with silicon devices. In this paper, elemental technologies such as interconnection of TSV, fabrication of fine wiring, and evaluation of interlayer dielectric are reported. Finally, the application of silicon interposer such as silicon module and inorganic-organic hybrid substrate, are described. As further evolution systems, a substrate with micro channel and substrate less package are proposed.

Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring

A semiconductor device, enabling reliable electrical connection of a main electrode pad with an interconnection pattern without separate provision of a via use electrode pad in addition to the existing main electrode pad, provided with a silicon substrate (semiconductor substrate), an electronic element formation layer formed on one surface of that silicon substrate, an electrode pad having an extension and electrically connected to the electronic element formation layer, a through hole passing through the electrode pad and the silicon substrate, an SiO2 film (insulating film), a via hole provided in the SiO2 film on the extension of the electrode pad, and an interconnection pattern electrically leading out the electrode pad to the other surface of the silicon substrate through the through hole and via hole, said through hole having a diameter larger at a portion passing through the electrode pad than a portion passing through the semiconductor substrate.

Semiconductor device and method of production of same

A process for producing a semiconductor device includes a step of forming an anisotropic conductive adhesive layer, which includes a thermoplastic or thermosetting resin and conductive powder dispersed therein, on a surface of a circuit board on which electrode terminal contacts are arranged so as to correspond to electrode terminals of a semiconductor chip which is to be mounted on said circuit board. Then, the anisotropic conductive adhesive layer is softened and the semiconductor chip is placed in such a manner that the electrode terminals coincide with the electrode terminal contacts through the anisotropic conductive adhesive layer. The semiconductor chip is heat-pressed against the circuit board so that the electrode terminals are electrically connected to the electrode terminal contacts and simultaneously the semiconductor chip is physically fixed to the circuit board when the anisotropic conductive adhesive layer is hardened.

Mitsutoshi Higashi

Papers

Electronic parts packaging structure and method of manufacturing the same

Semiconductor device having an element with circuit pattern thereon

Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring

Semiconductor device and method of production of same

Process for producing a semiconductor device using anisotropic conductive adhesive